公开(公告)号：US09842654B2

公开(公告)日：2017-12-12

申请号：US14996249

申请日：2016-01-15

申请人： Ji-Sang Lee ,  Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

发明人： Ji-Sang Lee ,  Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C11/56

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

摘要： A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

公开(公告)号：US20170062059A1

公开(公告)日：2017-03-02

申请号：US15245162

申请日：2016-08-23

申请人： Yoon KIM ,  Dong-chan KIM ,  Ji-sang LEE

发明人： Yoon KIM ,  Dong-chan KIM ,  Ji-sang LEE

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/349

摘要： A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

摘要翻译： 一种存储器件，包括：包括多个NAND串的存储单元阵列，每个NAND串包括分别连接到垂直堆叠在衬底上的多个字线的多个存储器单元; 以及控制逻辑，被配置为为NAND串的第一NAND串的存储器单元生成预编程控制信号，使得在擦除第一NAND串的存储单元之前，将预编程电压施加到耦合到 第一NAND串的对应存储单元基于相应的存储单元的工作特性而变化。

公开(公告)号：US20170011799A1

公开(公告)日：2017-01-12

申请号：US14996249

申请日：2016-01-15

申请人： JI-SANG LEE ,  DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

发明人： JI-SANG LEE ,  DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

IPC分类号： G11C16/10 ,  G11C16/24 ,  G11C16/04 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

摘要： A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

摘要翻译： 非易失性存储器包括存储单元阵列，行解码器电路和页缓冲电路。 行解码器电路响应于从外部设备接收到的写入命令，在第一预充电操作时，对连接到所选存储块的串选择晶体管的串选择线施加导通电压。 页缓冲器电路响应于写入命令，在第一预充电操作下，连接到串选择晶体管的第一电压至位线，而不管加载数据如何，并施加第一电压和 基于所加载的数据，在第二预充电操作中通过第二预充电电路对位线施加第二电压。 在第一预充电操作期间，写数据被加载到页缓冲电路。

公开(公告)号：US09053822B2

公开(公告)日：2015-06-09

申请号：US13777512

申请日：2013-02-26

申请人： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

发明人： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56

CPC分类号： G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

摘要： Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

摘要翻译： 操作非易失性存储器件的方法可以包括识别非易失性存储器件中的一个或多个多位非易失性存储器单元，其经历从擦除状态到至少部分编程状态的无意编程。 可以通过执行多个读取操作来生成错误检测数据，然后解码错误检测数据以识别具有错误的特定单元，来检测在编程第一多个多位非易失性存储器单元的操作期间产生的错误。 可以读取编程的第一多个多位非易失性存储单元和在编程操作期间被修改的强位数据向量，以支持错误检测。 然后可以将该数据连同从与第一多个多位非易失性存储器单元相关联的页面缓冲器读取的数据解码以识别第一多个多位非易失性存储器单元中的哪一个是无意编程的单元。

公开(公告)号：US08811094B2

公开(公告)日：2014-08-19

申请号：US13528886

申请日：2012-06-21

申请人： Ji-Sang Lee ,  Ki Hwan Choi

发明人： Ji-Sang Lee ,  Ki Hwan Choi

IPC分类号： G11C16/16 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/14

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3418

摘要： A non-volatile memory device, a data read method thereof and a recording medium are provided. The method includes receiving a data read command for a first word line in a memory cell array, reading data from a second word line adjacent to the first word line, and reading data from the first word line using a different voltage according to a state of the data read from the second word line. The number of read voltages used to distinguish an erased state and a first programmed state is greater than the number of read voltages used to distinguish a second programmed state and a third programmed state.

摘要翻译： 提供非易失性存储器件，其数据读取方法和记录介质。 该方法包括接收存储单元阵列中的第一字线的数据读取命令，从与第一字线相邻的第二字线读取数据，以及根据第一字线的状态从第一字线读取数据，使用不同的电压 从第二个字线读取数据。 用于区分擦除状态和第一编程状态的读取电压的数量大于用于区分第二编程状态和第三编程状态的读取电压的数量。

公开(公告)号：US08675416B2

公开(公告)日：2014-03-18

申请号：US13235533

申请日：2011-09-19

申请人： Ji-Sang Lee

发明人： Ji-Sang Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3459

摘要： A nonvolatile memory device performs a program operation using an incremental pulse programming (ISPP) scheme in which a plurality of program loops alternate between a coarse-fine verify operation, and a fine verify operation according to a value of a program loop counter.

摘要翻译： 非易失性存储器件使用增量脉冲编程（ISPP）方案来执行编程操作，其中多个程序循环根据程序循环计数器的值在粗细验证操作和精细校验操作之间交替。

公开(公告)号：US20130322171A1

公开(公告)日：2013-12-05

申请号：US13777512

申请日：2013-02-26

申请人： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

发明人： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

IPC分类号： G11C29/04 ,  G11C16/02

CPC分类号： G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

摘要： Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

公开(公告)号：US08537621B2

公开(公告)日：2013-09-17

申请号：US13094192

申请日：2011-04-26

申请人： Ji-Sang Lee ,  Kihwan Choi

发明人： Ji-Sang Lee ,  Kihwan Choi

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

摘要： In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled.

摘要翻译： 在一个实施例中，该方法包括接收读取存储在与第一字线相关联的第一存储器单元中的数据的请求，以及响应于该请求对与第二字线相关联的至少一个存储器单元执行第一读取操作。 第二字线在字线编程顺序中跟随第一字线，并且在第一时间段执行第一读取操作。 该方法还包括基于来自第一读取操作的输出对第一存储器单元执行第二读取操作。 如果从执行第一读取操作的输出指示第一存储器单元没有耦合，则第二次读取操作执行第二时间段，并且第一时间段比第二时间段短。

公开(公告)号：US20130039130A1

公开(公告)日：2013-02-14

申请号：US13568287

申请日：2012-08-07

申请人： Ji-Sang Lee

发明人： Ji-Sang Lee

IPC分类号： G11C16/10

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3459

摘要： Disclosed is a program method of a nonvolatile memory device including applying a first program voltage to a word line of a memory cell; verifying a variation of a threshold voltage of the memory cell; and applying a second program voltage to a memory cell having a threshold voltage higher than a reference level, the second program voltage being lower in level than the first voltage pulse.

摘要翻译： 公开了一种非易失性存储器件的编程方法，包括：将第一编程电压施加到存储单元的字线; 验证存储器单元的阈值电压的变化; 以及向具有高于参考电平的阈值电压的存储单元施加第二编程电压，所述第二编程电压的电平低于所述第一电压脉冲。

公开(公告)号：US20110305081A1

公开(公告)日：2011-12-15

申请号：US13053343

申请日：2011-03-22

申请人： Ji-Sang LEE

发明人： Ji-Sang LEE

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method of programming a nonvolatile memory device comprises programming target memory cells among a plurality of memory cells connected to a wordline, performing a first sensing operation on the plurality of memory cells, and selectively performing a second sensing operation on the target memory cells based on a result of the first sensing operation.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括在连接到字线的多个存储器单元中编程目标存储器单元，对所述多个存储器单元执行第一感测操作，并且基于所述目标存储器单元选择性地对所述目标存储器单元执行第二感测操作 这是第一感测操作的结果。