利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

26 条记录 (耗时 0.021 秒)

    Methods of operating nonvolatile memory devices that support efficient error detection
    1.
    发明授权
    Methods of operating nonvolatile memory devices that support efficient error detection 有权
    操作支持高效错误检测的非易失性存储器件的方法

    公开(公告)号：US09053822B2

    公开(公告)日：2015-06-09

    申请号：US13777512

    申请日：2013-02-26

    申请人： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

    发明人： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56

    CPC分类号： G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

    摘要： Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

    摘要翻译： 操作非易失性存储器件的方法可以包括识别非易失性存储器件中的一个或多个多位非易失性存储器单元，其经历从擦除状态到至少部分编程状态的无意编程。 可以通过执行多个读取操作来生成错误检测数据，然后解码错误检测数据以识别具有错误的特定单元，来检测在编程第一多个多位非易失性存储器单元的操作期间产生的错误。 可以读取编程的第一多个多位非易失性存储单元和在编程操作期间被修改的强位数据向量，以支持错误检测。 然后可以将该数据连同从与第一多个多位非易失性存储器单元相关联的页面缓冲器读取的数据解码以识别第一多个多位非易失性存储器单元中的哪一个是无意编程的单元。

    Nonvolatile memory devices operable using negative bias voltages and related methods of operation
    4.
    发明授权
    Nonvolatile memory devices operable using negative bias voltages and related methods of operation 有权
    可使用负偏置电压工作的非易失性存储器件和相关操作方法

    公开(公告)号：US08248852B2

    公开(公告)日：2012-08-21

    申请号：US12820628

    申请日：2010-06-22

    申请人： Moosung Kim ,  Youngho Lim

    发明人： Moosung Kim ,  Youngho Lim

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C16/34

    摘要： A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second well that is electrically isolated from the first well. The first and second address decoders are associated with first and second memory blocks, respectively. A switch circuit is configured to provide a negative voltage to one of the first address decoder and the second address decoder on the basis of block address information that specifies an address included in one of the first memory block and the second memory block. Related methods of operation are also discussed.

    摘要翻译： 非易失性存储器件包括第一地址解码器和第二地址解码器。 第一地址解码器包括设置在第一阱中的多个晶体管，并且第二地址译码器包括设置在与第一阱电绝缘的第二阱中的多个晶体管。 第一和第二地址解码器分别与第一和第二存储器块相关联。 开关电路被配置为基于指定包括在第一存储器块和第二存储器块之一中的地址的块地址信息来向第一地址译码器和第二地址译码器之一提供负电压。 还讨论了相关的操作方法。

    NONVOLATILE MEMORY DEVICES OPERABLE USING NEGATIVE BIAS VOLTAGES AND RELATED METHODS OF OPERATION
    5.
    发明申请
    NONVOLATILE MEMORY DEVICES OPERABLE USING NEGATIVE BIAS VOLTAGES AND RELATED METHODS OF OPERATION 有权
    使用负偏差电压运行的非易失性存储器件及相关操作方法

    公开(公告)号：US20110096602A1

    公开(公告)日：2011-04-28

    申请号：US12820628

    申请日：2010-06-22

    申请人： Moosung Kim ,  Youngho Lim

    发明人： Moosung Kim ,  Youngho Lim

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C16/34

    摘要： A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second well that is electrically isolated from the first well. The first and second address decoders are associated with first and second memory blocks, respectively. A switch circuit is configured to provide a negative voltage to one of the first address decoder and the second address decoder on the basis of block address information that specifies an address included in one of the first memory block and the second memory block. Related methods of operation are also discussed.

    摘要翻译： 非易失性存储器件包括第一地址解码器和第二地址解码器。 第一地址解码器包括设置在第一阱中的多个晶体管，并且第二地址译码器包括设置在与第一阱电绝缘的第二阱中的多个晶体管。 第一和第二地址解码器分别与第一和第二存储器块相关联。 开关电路被配置为基于指定包括在第一存储器块和第二存储器块之一中的地址的块地址信息来向第一地址译码器和第二地址译码器之一提供负电压。 还讨论了相关的操作方法。

    Nonvolatile memory device, driving method thereof, and memory system having the same
    6.
    发明授权
    Nonvolatile memory device, driving method thereof, and memory system having the same 有权
    非易失性存储器件，其驱动方法和具有该非易失性存储器件的存储器系统

    公开(公告)号：US08488384B2

    公开(公告)日：2013-07-16

    申请号：US13478717

    申请日：2012-05-23

    申请人： Moosung Kim

    发明人： Moosung Kim

    IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/30

    CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/565

    摘要： A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and a ground voltage is applied to the well of the transistor. And, during a second time a second high voltage level is applied to the channel of the transistor, and within the second time interval a first negative voltage is applied to the well of the transistor. The first high voltage level is higher than the second high voltage level, and a voltage applied on the selected wordline is negative within the second time interval.

    摘要翻译： 非易失性存储器件（NVM），存储器系统和装置包括控制逻辑，其被配置为执行在NVM的选定字线上施加负电压的方法。 在第一时间内，将第一高电压电平施加到地址解码器的晶体管的通道，并将接地电压施加到晶体管的阱。 并且，在第二时间中，第二高电压电平施加到晶体管的沟道，并且在第二时间间隔内，第一负电压被施加到晶体管的阱。 第一高电压电平高于第二高电压电平，施加在所选字线上的电压在第二时间间隔内为负。

    Nonvolatile Memory Devices Having Memory Cell Arrays with Unequal-Sized Memory Cells and Methods of Operating Same
    8.
    发明申请
    Nonvolatile Memory Devices Having Memory Cell Arrays with Unequal-Sized Memory Cells and Methods of Operating Same 有权
    具有不等尺寸存储单元的存储单元阵列的非易失性存储器件和操作方法相同

    公开(公告)号：US20110222348A1

    公开(公告)日：2011-09-15

    申请号：US13035369

    申请日：2011-02-25

    申请人： Moosung Kim ,  Sungsoo Lee

    发明人： Moosung Kim ,  Sungsoo Lee

    IPC分类号： G11C16/10

    CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/10

    摘要： Nonvolatile memory devices include a two-dimensional array of nonvolatile memory cells having a plurality of memory cells of unequal size therein. These memory cells may include those that have unequal channel widths associated with respective word lines and those having unequal channel lengths associated with respective bit lines that are connected to corresponding strings of nonvolatile memory cells (e.g., NAND-type strings). Control circuitry is also provided that is electrically coupled to the two-dimensional array of nonvolatile memory cells. This control circuitry may operate to concurrently program first and second nonvolatile memory cells having unequal sizes from an erased state (e.g., logic 1) to an equivalent programmed state (e.g., logic 0). This is done by establishing unequal first and second word line-to-channel region voltages in the first and second nonvolatile memory cells, respectively, during an operation to program a row of memory cells in the two-dimensional array of nonvolatile memory cells, which includes the first and second nonvolatile memory cells of unequal size.

    摘要翻译： 非易失性存储器件包括其中具有不同尺寸的多个存储单元的非易失性存储单元的二维阵列。 这些存储器单元可以包括具有与相应字线相关联的不相等通道宽度的那些存储器单元，以及具有与连接到非易失性存储器单元（例如，NAND型串）的相应串的各个位线相关联的不相等的通道长度的存储器单元）。 还提供了电耦合到非易失性存储器单元的二维阵列的控制电路。 该控制电路可以操作以将具有不同大小的第一和第二非易失性存储器单元从擦除状态（例如，逻辑1）同时编程为等效的编程状态（例如，逻辑0）。 这是通过在对非易失性存储器单元的二维阵列中的一行存储器单元进行编程的操作期间分别在第一和第二非易失性存储器单元中建立不相等的第一和第二字线到沟道区域电压来实现的， 包括不等大小的第一和第二非易失性存储单元。

    Flash memory device and wordline voltage generating method thereof
    10.
    发明授权
    Flash memory device and wordline voltage generating method thereof 有权
    闪存装置及其字线电压产生方法

    公开(公告)号：US08559229B2

    公开(公告)日：2013-10-15

    申请号：US13246040

    申请日：2011-09-27

    申请人： Seung-Gum Kim ,  Ohsuk Kwon ,  Dongku Kang ,  Tae-Young Kim ,  Jaewoo Im ,  Moosung Kim ,  Jae-Duk Yu

    发明人： Seung-Gum Kim ,  Ohsuk Kwon ,  Dongku Kang ,  Tae-Young Kim ,  Jaewoo Im ,  Moosung Kim ,  Jae-Duk Yu

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/30 ,  G11C16/3436

    摘要： A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative voltage generator; and generating at least one or more program verification voltages corresponding to at least one or more states using the positive voltage generator. Generating a plurality of negative program verification voltages includes generating a first negative verification voltage; discharging an output of the negative voltage generator to become higher than the first negative verification voltage; and performing a negative charge pumping operation until an output of the negative voltage generator reaches a second negative verification voltage level.

    摘要翻译： 一种闪存的字线电压产生方法，包括使用正电压发生器产生编程电压; 使用负电压发生器产生对应于多个负数据状态的多个负编程验证电压; 以及使用所述正电压发生器产生对应于至少一个或多个状态的至少一个或多个程序验证电压。 生成多个负编程验证电压包括产生第一负验证电压; 将负电压发生器的输出放电到高于第一负验证电压; 并执行负电荷泵送操作直到负电压发生器的输出达到第二负验证电压电平。