摘要:
An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.
摘要:
A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
摘要:
A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
摘要:
A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要:
A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要:
A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要:
A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要:
An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.
摘要:
A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.
摘要:
A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.