公开(公告)号：US20130193492A1

公开(公告)日：2013-08-01

申请号：US13360823

申请日：2012-01-30

申请人： THOMAS N. ADAM ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

发明人： THOMAS N. ADAM ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L21/0245 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7848

摘要： An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.

摘要翻译： 公开了一种改进的硅碳膜结构。 膜结构包括多层硅碳和硅。 多层形成具有增加的取代碳含量的应力膜结构，并且用于诱导改善某些类型的场效应晶体管的载流子迁移率的应力。

公开(公告)号：US09190471B2

公开(公告)日：2015-11-17

申请号：US13446350

申请日：2012-04-13

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/84

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/84 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/78

摘要： A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.

摘要翻译： 包括半导体晶片的半导体结构。 所述半导体晶片包括栅极结构，所述半导体晶片中与所述栅极结构的第一侧相邻的第一沟槽和与所述栅极结构的第二侧相邻的第二沟槽，所述第一和第二沟槽填充有掺杂的外延硅， 在填充的第一沟槽中形成源极，并且在填充的第二沟槽中形成漏极，使得源极和漏极中的每一个凹入并具有倒置的面。 在优选的示例性实施例中，外延硅掺杂有硼。

公开(公告)号：US20130270611A1

公开(公告)日：2013-10-17

申请号：US13446350

申请日：2012-04-13

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/84 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/78

摘要： A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.

摘要翻译： 包括半导体晶片的半导体结构。 所述半导体晶片包括栅极结构，所述半导体晶片中与所述栅极结构的第一侧相邻的第一沟槽和与所述栅极结构的第二侧相邻的第二沟槽，所述第一和第二沟槽填充有掺杂的外延硅， 在填充的第一沟槽中形成源极，并且在填充的第二沟槽中形成漏极，使得源极和漏极中的每一个凹入并具有倒置的面。 在优选的示例性实施例中，外延硅掺杂有硼。

公开(公告)号：US08946033B2

公开(公告)日：2015-02-03

申请号：US13561352

申请日：2012-07-30

申请人： Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L29/16 ,  H01L29/161 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795

摘要： A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.

摘要翻译： 翅片finFET和其制造方法。 鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面 并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

公开(公告)号：US20140027863A1

公开(公告)日：2014-01-30

申请号：US13561352

申请日：2012-07-30

申请人： Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/16 ,  H01L29/161 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795

摘要： A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.

摘要翻译： 翅片finFET和其制造方法。 鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面 并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

公开(公告)号：US20120305940A1

公开(公告)日：2012-12-06

申请号：US13151238

申请日：2011-06-01

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

IPC分类号： H01L29/24 ,  H01L21/20

CPC分类号： H01L21/02529 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.

摘要翻译： 公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。 接受具有{100}晶体取向的主表面的晶片。 以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。 外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

公开(公告)号：US20100200896A1

公开(公告)日：2010-08-12

申请号：US12367561

申请日：2009-02-09

申请人： Thomas N. Adam ,  Jinghong Li ,  Thomas A. Wallner ,  Haizhou Yin

发明人： Thomas N. Adam ,  Jinghong Li ,  Thomas A. Wallner ,  Haizhou Yin

IPC分类号： H01L29/04 ,  H01L21/20 ,  H01L29/161

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02573 ,  H01L21/78 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for growing an epitaxial layer on a substrate wherein the substrate includes a surface having a Miller index of (110) for the beneficial properties. The method comprises using a direct silicon bonded wafer with a substrate having a first Miller index and a surface having a second Miller index. An element such as a gate for a PFET may be deposited onto the surface. The area not under the gate may then be etched away to expose the substrate. An epitaxial layer may then be grown on the surface providing optimal growth patterns. The Miller index of the substrate may be (100). In an alternative embodiment the surface may have a Miller index of (100) and the surface is etched where an element such as a gate for a PFET may be placed.

摘要翻译： 一种用于在衬底上生长外延层的方法，其中所述衬底包括具有用于有益特性的（110）的米勒指数的表面。 该方法包括使用具有第一米勒指数的基底和具有第二米勒指数的表面的直接硅键合晶片。 诸如用于PFET的栅极的元件可以沉积在表面上。 然后可以蚀刻掉不在栅极下方的区域以露出衬底。 然后可以在表面上生长外延层，提供最佳生长模式。 基板的米勒指数可以是（100）。 在替代实施例中，表面可以具有（100）的米勒指数，并且表面被蚀刻，其中可以放置诸如用于PFET的栅极的元件。

公开(公告)号：US08035141B2

公开(公告)日：2011-10-11

申请号：US12607104

申请日：2009-10-28

申请人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

摘要翻译： 公开了一种包括双层nFET嵌入式应力元件的半导体结构。 双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。 双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变 。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。 双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。 双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

公开(公告)号：US08421191B2

公开(公告)日：2013-04-16

申请号：US13533499

申请日：2012-06-26

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L31/117

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

摘要翻译： 公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。 所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。 每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。 至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

公开(公告)号：US20110095343A1

公开(公告)日：2011-04-28

申请号：US12607104

申请日：2009-10-28

申请人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

摘要翻译： 公开了一种包括双层nFET嵌入式应力元件的半导体结构。 双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。 双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变 。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。 双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。 双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。