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    Semiconductor devices including interlayer conductive contacts and methods of forming the same
    1.
    发明授权
    Semiconductor devices including interlayer conductive contacts and methods of forming the same 有权
    包括层间导电触点的半导体器件及其形成方法

    公开(公告)号：US07888798B2

    公开(公告)日：2011-02-15

    申请号：US12080284

    申请日：2008-04-02

    申请人： Jongwon Hong ,  GeumJung Seong ,  Jongmyeong Lee ,  Hyunbae Lee ,  Bonghyun Choi

    发明人： Jongwon Hong ,  GeumJung Seong ,  Jongmyeong Lee ,  Hyunbae Lee ,  Bonghyun Choi

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/115 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.

    摘要翻译： 在半导体器件及其形成方法中，半导体器件包括：在半导体器件的下部接触区域上的第一绝缘层，第一绝缘层具有上表面; 在通过第一绝缘层的第一开口中的第一导电图案，第一导电图案的上部具有第一宽度，第一导电图案的上表面相对于第一绝缘层的上表面凹陷，使得 第一导电图案的上表面相对于下面的接触区域具有相对于下面的接触区域小于第一绝缘层的上表面的高度的高度; 以及与第一导电图案的上表面接触的第二导电图案，第二导电图案的下部具有小于第一宽度的第二宽度。

    Metal interconnect of semiconductor device
    2.
    发明授权
    Metal interconnect of semiconductor device 有权
    半导体器件的金属互连

    公开(公告)号：US08319348B2

    公开(公告)日：2012-11-27

    申请号：US12722643

    申请日：2010-03-12

    申请人： Jongmyeong Lee ,  Zungsun Choi ,  Gilheyun Choi ,  Byung-Lyul Park ,  Jinho Park ,  Hye Kyung Jung

    发明人： Jongmyeong Lee ,  Zungsun Choi ,  Gilheyun Choi ,  Byung-Lyul Park ,  Jinho Park ,  Hye Kyung Jung

    IPC分类号： H01L23/48

    CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device.

    摘要翻译： 提供半导体器件的金属互连和制造金属互连的方法。 金属互连包括金属线，其具有设置在与第一端相对的第一端和第二端，电连接到金属线的通孔和从第一端延伸并且包括空隙的非活性段。 减小拉伸应力以防止孔下方发生空隙。 因此，基本上防止了电迁移引起的线路断线，从而提高了器件的电气特性。

    Semiconductor devices including interlayer conductive contacts and methods of forming the same
    4.
    发明授权
    Semiconductor devices including interlayer conductive contacts and methods of forming the same 有权
    包括层间导电触点的半导体器件及其形成方法

    公开(公告)号：US08404593B2

    公开(公告)日：2013-03-26

    申请号：US12984838

    申请日：2011-01-05

    申请人： Jongwon Hong ,  GeumJung Seong ,  Jongmyeong Lee ,  Hyunbae Lee ,  Bonghyun Choi

    发明人： Jongwon Hong ,  GeumJung Seong ,  Jongmyeong Lee ,  Hyunbae Lee ,  Bonghyun Choi

    IPC分类号： H01L21/311

    CPC分类号： H01L27/115 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.

    摘要翻译： 在半导体器件及其形成方法中，半导体器件包括：在半导体器件的下部接触区域上的第一绝缘层，第一绝缘层具有上表面; 在通过第一绝缘层的第一开口中的第一导电图案，第一导电图案的上部具有第一宽度，第一导电图案的上表面相对于第一绝缘层的上表面凹陷，使得 第一导电图案的上表面相对于下面的接触区域具有相对于下面的接触区域小于第一绝缘层的上表面的高度的高度; 以及与第一导电图案的上表面接触的第二导电图案，第二导电图案的下部具有小于第一宽度的第二宽度。

    Semiconductor devices including interlayer conductive contacts and methods of forming the same
    7.
    发明申请
    Semiconductor devices including interlayer conductive contacts and methods of forming the same 有权
    包括层间导电触点的半导体器件及其形成方法

    公开(公告)号：US20080284006A1

    公开(公告)日：2008-11-20

    申请号：US12080284

    申请日：2008-04-02

    申请人： Jongwon Hong ,  GeumJung Seong ,  Jongmyeong Lee ,  Hyunbae Lee ,  Bonghyun Choi

    发明人： Jongwon Hong ,  GeumJung Seong ,  Jongmyeong Lee ,  Hyunbae Lee ,  Bonghyun Choi

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L27/115 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.

    摘要翻译： 在半导体器件及其形成方法中，半导体器件包括：在半导体器件的下部接触区域上的第一绝缘层，第一绝缘层具有上表面; 在通过第一绝缘层的第一开口中的第一导电图案，第一导电图案的上部具有第一宽度，第一导电图案的上表面相对于第一绝缘层的上表面凹陷，使得 第一导电图案的上表面相对于下面的接触区域具有相对于下面的接触区域小于第一绝缘层的上表面的高度的高度; 以及与第一导电图案的上表面接触的第二导电图案，第二导电图案的下部具有小于第一宽度的第二宽度。

    Semiconductor Device and Method for Forming the Same
    10.
    发明申请
    Semiconductor Device and Method for Forming the Same 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20110195569A1

    公开(公告)日：2011-08-11

    申请号：US13024899

    申请日：2011-02-10

    申请人： Kwangjin Moon ,  Gilheyun Choi ,  Jongmyeong Lee ,  Zungsun Choi ,  Hye Kyung Jung

    发明人： Kwangjin Moon ,  Gilheyun Choi ,  Jongmyeong Lee ,  Zungsun Choi ,  Hye Kyung Jung

    IPC分类号： H01L21/768

    CPC分类号： H01L21/288 ,  H01L21/28562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/7685 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： Methods of forming field effect transistors include forming a metal alloy gate electrode (e.g., aluminum alloy) containing about 0.5 to about 1.0 atomic percent silicon, on a substrate, and electroless plating an electrically conductive gate protection layer directly on at least a portion of an upper surface of the metal alloy gate electrode. A gate dielectric layer may be formed on the substrate. This gate dielectric layer may have a dielectric constant greater than a dielectric constant of silicon dioxide. The forming of the metal alloy gate electrode may include forming a metal alloy gate electrode directly on an upper surface of the gate dielectric layer.

    摘要翻译： 形成场效应晶体管的方法包括在衬底上形成含有约0.5至约1.0原子％硅的金属合金栅电极（例如，铝合金），以及直接在至少一部分硅上的电导电栅极保护层 金属合金栅电极的上表面。 栅电介质层可以形成在衬底上。 该栅介电层可具有大于二氧化硅介电常数的介电常数。 金属合金栅电极的形成可以包括在栅介质层的上表面上直接形成金属合金栅电极。