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    Metal interconnect of semiconductor device
    1.
    发明授权
    Metal interconnect of semiconductor device 有权
    半导体器件的金属互连

    公开(公告)号：US08319348B2

    公开(公告)日：2012-11-27

    申请号：US12722643

    申请日：2010-03-12

    申请人： Jongmyeong Lee ,  Zungsun Choi ,  Gilheyun Choi ,  Byung-Lyul Park ,  Jinho Park ,  Hye Kyung Jung

    发明人： Jongmyeong Lee ,  Zungsun Choi ,  Gilheyun Choi ,  Byung-Lyul Park ,  Jinho Park ,  Hye Kyung Jung

    IPC分类号： H01L23/48

    CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device.

    摘要翻译： 提供半导体器件的金属互连和制造金属互连的方法。 金属互连包括金属线，其具有设置在与第一端相对的第一端和第二端，电连接到金属线的通孔和从第一端延伸并且包括空隙的非活性段。 减小拉伸应力以防止孔下方发生空隙。 因此，基本上防止了电迁移引起的线路断线，从而提高了器件的电气特性。

    Metal Interconnect of Semiconductor Device
    2.
    发明申请
    Metal Interconnect of Semiconductor Device 有权
    半导体器件的金属互连

    公开(公告)号：US20100230824A1

    公开(公告)日：2010-09-16

    申请号：US12722643

    申请日：2010-03-12

    申请人： Jongmyeong Lee ,  Zungsun Choi ,  Gilheyun Choi ,  Byung-Lyul Park ,  Jinho Park ,  Hye Kyung Jung

    发明人： Jongmyeong Lee ,  Zungsun Choi ,  Gilheyun Choi ,  Byung-Lyul Park ,  Jinho Park ,  Hye Kyung Jung

    IPC分类号： H01L23/48

    CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device.

    摘要翻译： 提供半导体器件的金属互连和制造金属互连的方法。 金属互连包括金属线，其具有设置在与第一端相对的第一端和第二端，电连接到金属线的通孔和从第一端延伸并且包括空隙的非活性段。 减小拉伸应力以防止孔下方发生空隙。 因此，基本上防止了电迁移引起的线路断线，从而提高了器件的电气特性。

    Method of manufacturing a semiconductor device
    4.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08696921B2

    公开(公告)日：2014-04-15

    申请号：US12687987

    申请日：2010-01-15

    申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

    发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

    IPC分类号： H01L21/302

    CPC分类号： H01L21/6719 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76877

    摘要： In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

    摘要翻译： 在制造半导体器件的方法中，将衬底装载到具有分别执行单元处理的单元处理部的处理室。 单元处理在相应的处理压力下在单元处理部分彼此独立地在衬底上进行。 基板在处理室的各单元处理部分依次进行单元处理。 当从每个单元处理部分传送基板并且没有基板位于单元处理部分时，分别对单元处理部分进行清洁处理。 因此，可以充分防止处理单元的处理缺陷，并且制造装置的操作周期充分延长。

    Photoelectric Integrated Circuit Devices And Methods Of Forming The Same
    8.
    发明申请
    Photoelectric Integrated Circuit Devices And Methods Of Forming The Same 审中-公开
    光电集成电路器件及其形成方法

    公开(公告)号：US20120039564A1

    公开(公告)日：2012-02-16

    申请号：US13191874

    申请日：2011-07-27

    申请人： Pil-Kyu Kang ,  GilHeyun Choi ,  Sukchul Bang ,  Daelok Bae ,  Byung-Lyul Park ,  KwangJin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

    发明人： Pil-Kyu Kang ,  GilHeyun Choi ,  Sukchul Bang ,  Daelok Bae ,  Byung-Lyul Park ,  KwangJin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

    IPC分类号： G02B6/12

    CPC分类号： G02B6/131 ,  G02B6/132 ,  G02B6/136 ,  G02B2006/12061

    摘要： A photoelectric integrated circuit device may include a substrate including an electronic device region and an on die optical input/output device region, the substrate having a trench in the on die optical input/output device region; a lower clad layer provided in the trench, the lower clad layer having an upper surface lower than a surface of the substrate; a core provided on the lower clad layer; an insulating pattern provided on the core; an optical detection pattern provided on the insulating pattern, the optical detection pattern having at least a portion provided in the trench; and at least one transistor provided on the substrate of the electronic device region.

    摘要翻译： 光电集成电路器件可以包括包括电子器件区域和裸片上的光输入/输出器件区域的衬底，所述衬底在管芯光输入/输出器件区域中具有沟槽; 设置在所述沟槽中的下包层，所述下包层具有比所述基板的表面低的上表面; 设置在下包层上的芯; 设置在芯上的绝缘图案; 设置在所述绝缘图案上的光学检测图案，所述光学检测图案具有设置在所述沟槽中的至少一部分; 以及设置在电子器件区域的衬底上的至少一个晶体管。