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11 条记录 (耗时 0.013 秒)

    Field programmable device having test provisions for fault detection
    2.
    发明授权
    Field programmable device having test provisions for fault detection 失效
    具有故障检测测试条件的现场可编程器件

    公开(公告)号：US4320507A

    公开(公告)日：1982-03-16

    申请号：US95782

    申请日：1979-11-19

    申请人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    发明人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    IPC分类号： G11C17/00 ,  G11C29/00 ,  G11C29/24 ,  G11C29/52 ,  G06F11/22 ,  G01R31/26

    CPC分类号： G11C29/52 ,  G11C29/24

    摘要： A field programmable device having a memory cell member including regular bit lines, regular word lines, regular memory cells connected at the cross points of said regular bit lines and regular word lines, test bit or test word lines, and non-conductive and conductive test memory cells connected at the cross points of said regular bit or regular word lines and test word or test bit lines, wherein the conductivity of a test memory cell is determined by the "1" or "0" of the address signal by which the test word or test bit line to which the test memory cell is connected is selected.

    摘要翻译： 一种具有存储单元构件的现场可编程装置，包括常规位线，常规字线，在所述规则位线和规则字线的交叉点处连接的常规存储单元，测试位或测试字线，以及非导电和导电测试 在所述规则位或常规字线和测试字或测试位线的交叉点处连接的存储单元，其中测试存储单元的电导率由地址信号的“1”或“0”确定， 选择测试存储单元连接到的字或测试位线。

    Data processor including selection mechanism for coupling internal and external request signals to interrupt and DMA controllers
    3.
    发明授权
    Data processor including selection mechanism for coupling internal and external request signals to interrupt and DMA controllers 失效
    数据处理器包括用于将内部和外部请求信号耦合到中断和DMA控制器的选择机制

    公开(公告)号：US5481678A

    公开(公告)日：1996-01-02

    申请号：US92021

    申请日：1993-07-12

    申请人： Hiroyuki Kondo ,  Yuichi Nakao ,  Kazumi Koyama

    发明人： Hiroyuki Kondo ,  Yuichi Nakao ,  Kazumi Koyama

    IPC分类号： G06F13/00 ,  G06F13/32 ,  H04L29/10

    CPC分类号： G06F13/32

    摘要： A data processor includes an interrupt control unit (102); a direct memory access control unit (103); a selection unit (104) for selecting a connection of ready and error signals from a serial communication control unit and external interrupt and DMA request signals with interrupt inputs to the interrupt and the DMA control units; and a selection setting unit (105) for setting a selection mode of the selection unit, thereby making possible to not only switch between a process by interrupt and a process by DMA transfer by programming according to the application but also make efficient use of the hardware resources in the data processor.

    摘要翻译： 数据处理器包括中断控制单元（102）; 直接存储器访问控制单元（103）; 选择单元（104），用于选择来自串行通信控制单元的就绪和错误信号的连接以及具有对中断和DMA控制单元的中断输入的外部中断和DMA请求信号; 以及用于设置选择单元的选择模式的选择设置单元（105），从而不仅可以通过根据应用的编程通过中断和通过DMA传输的处理来切换处理，而且还有效地使用硬件 数据处理器中的资源。

    Programmable read-only memory device
    5.
    发明授权
    Programmable read-only memory device 失效
    可编程只读存储器件

    公开(公告)号：US4376984A

    公开(公告)日：1983-03-15

    申请号：US137959

    申请日：1980-04-07

    申请人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    发明人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    IPC分类号： G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L21/8229 ,  H01L23/525 ,  H01L27/10 ,  H01L27/102 ,  H01L29/45 ,  G11C11/40

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L27/10 ,  H01L29/456 ,  H01L2924/0002

    摘要： A PROM (programmable read-only memory) device includes both PROM cells and peripheral circuits cooperating therewith with the PROM cells and peripheral circuits formed in and on the same bulk. The bulk is formed free of metal which acts as a life time killer. Further, in each of the PROM cells, a buffer layer made of a silicon semiconductor, is introduced between a metal electrode, acting as a bit line, and the surface of the bulk at the position where the PROM cell is formed. Furthermore, the peripheral circuits are made by using Schottky TTL (transistor transistor logic) circuits.

    摘要翻译： PROM（可编程只读存储器）装置包括PROM单元和与PROM单元协同工作的外围电路和在相同体积上形成的外围电路。 该体积不含作为寿命杀手的金属。 此外，在每个PROM单元中，将由硅半导体制成的缓冲层引入作为位线的金属电极和在形成PROM单元的位置处的体的表面之间。 此外，通过使用肖特基TTL（晶体管晶体管逻辑）电路来制造外围电路。

    Programming circuit for permanently storing data in a programmable read only memory
    6.
    发明授权
    Programming circuit for permanently storing data in a programmable read only memory 失效
    用于将数据永久存储在可编程只读存储器中的编程电路

    公开(公告)号：US4319341A

    公开(公告)日：1982-03-09

    申请号：US141933

    申请日：1980-04-21

    申请人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno ,  Tamio Miyamura ,  Yuichi Kawabata

    发明人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno ,  Tamio Miyamura ,  Yuichi Kawabata

    IPC分类号： G11C17/00 ,  G11C17/06 ,  G11C17/08 ,  G11C17/14 ,  G11C17/18 ,  G11C7/00

    CPC分类号： G11C17/18 ,  G11C17/08

    摘要： A program circuit for permanently storing data into a programmable read only memory. A programming current (received from an external source) is connected to the selected bit line through a Darlington pair which is controlled by the bit decoding circuitry. Thus, the bit decoding circuitry is not required to pass the large programming current, and the programming current is not significantly shunted away from the selected bit line. To facilitate use of the Darlington configuration, a constant current source is provided for each bit line within a set of bit lines. The program circuit includes at least one switching means for connecting the program current to a selected bit line, a bit decoder connected to the control inputs of the switching means for selecting a bit line in response to the addressing signals input to the bit decoder and a control current supplying means for supplying a control current to the control inputs of the switching means.

    摘要翻译： 一种用于将数据永久存储到可编程只读存储器中的程序电路。 编程电流（从外部源接收）通过由位解码电路控制的达林顿对连接到所选择的位线。 因此，位解码电路不需要传递大的编程电流，并且编程电流没有被显着地分流离开所选择的位线。 为了方便使用达林顿配置，为一组位线内的每个位线提供恒流源。 程序电路包括用于将编程电流连接到所选位线的至少一个开关装置，连接到开关装置的控制输入的位解码器，用于响应于输入到位解码器的寻址信号选择位线，以及 用于向控制输入端提供控制电流的控制电流供给装置。

    Wait control device
    7.
    发明授权
    Wait control device 失效
    等待控制设备

    公开(公告)号：US5325521A

    公开(公告)日：1994-06-28

    申请号：US146473

    申请日：1993-11-01

    申请人： Kazumi Koyama ,  Yuichi Nakao

    发明人： Kazumi Koyama ,  Yuichi Nakao

    IPC分类号： G06F11/30 ,  G06F11/00 ,  G06F13/00 ,  G05F11/34

    CPC分类号： G06F11/0757

    摘要： A wait control device according to the present invention instructs a central processing unit (CPU) to wait for the start of its operation until the device receives a process completion signal from a memory unit or an I/O unit, and comprises setting means for setting the time of said CPU to wait for the start of its operation in the memory unit or the I/O unit accessed by the CPU, judgement means for judging system operation to be time out error when no process completion signal is presented during said time of the CPU, and selector means for selecting whether it passes a signal concerning the judgement of the time out error or successively waits for said processing completion signal.

    摘要翻译： 根据本发明的等待控制装置指令中央处理单元（CPU）等待其操作的开始，直到设备从存储器单元或I / O单元接收到处理完成信号，并且包括设置装置 所述CPU等待其在存储器单元或由CPU访问的I / O单元中的操作开始的时间;判断装置，用于在所述时间期间当没有处理完成信号被呈现时判断系统操作为超时错误 CPU和选择器装置，用于选择是否通过与超时错误的判断有关的信号，或者连续地等待所述处理完成信号。

    Field programmable device with circuitry for detecting poor insulation between adjacent word lines
    9.
    发明授权
    Field programmable device with circuitry for detecting poor insulation between adjacent word lines 失效
    具有用于检测相邻字线之间绝缘不良的电路的现场可编程器件

    公开(公告)号：US4459694A

    公开(公告)日：1984-07-10

    申请号：US333653

    申请日：1981-12-23

    申请人： Kouji Ueno ,  Toshitaka Fukushima ,  Kazumi Koyama

    发明人： Kouji Ueno ,  Toshitaka Fukushima ,  Kazumi Koyama

    IPC分类号： G11C29/00 ,  G11C17/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8229 ,  H01L27/04 ,  H01L27/102 ,  G06F11/22

    CPC分类号： G11C29/24 ,  G11C29/04

    摘要： A field programmable device comprises regular word lines, regular bit lines, regular memory cells connected at the intersections of the regular word lines and the regular bit lines, at least one test word line adjacent to one of the regular bit lines, and alternately arranged conducting and nonconducting test memory cells arranged at the intersections of the test bit lines and the regular word lines. According to the invention, for the purpose of determining poor insulation between the word lines, the test bit line and the regular word line are insulated by an insulating layer in each nonconducting test memory cell.

    摘要翻译： 现场可编程设备包括常规字线，规则位线，连接在正常字线和规则位线的交点处的常规存储器单元，至少一个与常规位线之一相邻的测试字线，并且交替排列导电 以及布置在测试位线和常规字线的交点处的非导体测试存储单元。 根据本发明，为了确定字线之间的差的绝缘，测试位线和常规字线在每个非导通测试存储单元中被绝缘层绝缘。