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    Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array
    1.
    发明授权
    Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array 失效
    用于在存储器阵列上启用时钟同步的读 - 修改 - 写操作的方法和电路

    公开(公告)号：US06745302B1

    公开(公告)日：2004-06-01

    申请号：US09394039

    申请日：1999-09-13

    申请人： Kazuo Taniguchi ,  Masaharu Yoshimori

    发明人： Kazuo Taniguchi ,  Masaharu Yoshimori

    IPC分类号： G06F1206

    CPC分类号： G11C8/18 ,  G11C7/1072

    摘要： A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplished in a pipeline manner by the basic synchronized pulse.

    摘要翻译： 一种能够进行数据读取修改写入操作的半导体存储器，包括：存储单元阵列，包括以矩阵形式布置并能够写入和读出数据的多个存储器单元; 读地址解码装置，用于响应于读地址独立地解码读存储单元的地址; 写地址解码装置，用于响应于写地址独立地解码写存储单元的地址; 数据读取装置，用于读取由读取地址解码装置寻址的存储单元的数据; 数据写入装置，用于将数据写入由写入地址解码装置寻址的存储单元; 以及地址延迟装置，由写地址解码装置解码的写地址从读地址解码装置解码的读地址延迟预定时间，其中预定时间被设置为预定的多次基本同步 脉冲周期，使得数据读取修改写入操作以流水线方式通过基本同步脉冲来实现。

    Shared memory device
    4.
    发明授权
    Shared memory device 失效
    共享内存设备

    公开(公告)号：US07536516B2

    公开(公告)日：2009-05-19

    申请号：US11344080

    申请日：2006-02-01

    申请人： Goragot Wongpaisarnsin ,  Kazuo Taniguchi ,  Masayuki Miyabayashi

    发明人： Goragot Wongpaisarnsin ,  Kazuo Taniguchi ,  Masayuki Miyabayashi

    IPC分类号： G06F13/28

    CPC分类号： G06F15/167

    摘要： A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and memory macro and transfers information with a memory control unit of a different memory system; the memory macro of each of the memory systems has a memory interface capable of transferring data; and the memory interfaces of the memory macros of different memory systems are mutually connected.

    摘要翻译： 一种共享存储装置，其能够简化与存储器的布线，防止由于区域的增加而导致的性能下降，并且延长布线，提高了系统的可扩展性的可扩展性。其中，该装置具有多个存储器系统，每个存储器系统包括 存储器宏，处理器和用于控制对存储器宏的访问的存储器控​​制单元; 其中每个存储器系统的存储器控​​制单元在处理器和存储器宏之间传送信息，并且与不同存储器系统的存储器控​​制单元传送信息; 每个存储器系统的存储器宏具有能够传送数据的存储器接口; 并且不同存储器系统的存储器宏的存储器接口相互连接。

    Test circuit and test method for semiconductor memory
    6.
    发明授权
    Test circuit and test method for semiconductor memory 失效
    半导体存储器的测试电路和测试方法

    公开(公告)号：US6134161A

    公开(公告)日：2000-10-17

    申请号：US942298

    申请日：1997-10-01

    申请人： Kazuo Taniguchi ,  Atsushi Tamura ,  Ken Matsumoto

    发明人： Kazuo Taniguchi ,  Atsushi Tamura ,  Ken Matsumoto

    IPC分类号： G11C11/401 ,  G11C29/02 ,  G11C29/40 ,  G11C29/48 ,  G11C7/00

    CPC分类号： G11C29/1201 ,  G11C29/40 ,  G11C29/48 ,  G11C11/401 ,  G11C2029/0401

    摘要： A logic IC including an embedded memory is provided with a test circuit therein which allows the embedded memory to be tested by using only three additional external pins of the logic IC for test purposes without regard to the bit count of a unit in which data is written into or read out from the embedded memory. In addition, the embedded memory can be tested by adopting a method that requires a period of testing time shorter than the related art one.

    摘要翻译： 包括嵌入式存储器的逻辑IC提供有其中的测试电路，其允许通过仅使用逻辑IC的三个附加外部引脚用于测试目的来测试嵌入式存储器，而不考虑其中写入数据的单元的位计数 从嵌入式存储器进入或读出。 此外，嵌入式存储器可以通过采用需要比现有技术时间短的测试时间的方法来测试。

    Apparatus and method for storing and accessing picture generation data
    7.
    发明授权
    Apparatus and method for storing and accessing picture generation data 失效
    用于存储和访问图像生成数据的装置和方法

    公开(公告)号：US6040844A

    公开(公告)日：2000-03-21

    申请号：US899925

    申请日：1997-07-24

    申请人： Yuji Yamaguchi ,  Masaharu Yoshimori ,  Hiroyuki Ozawa ,  Ryohei Iida ,  Kazuo Taniguchi

    发明人： Yuji Yamaguchi ,  Masaharu Yoshimori ,  Hiroyuki Ozawa ,  Ryohei Iida ,  Kazuo Taniguchi

    IPC分类号： G06T15/10 ,  G06F12/06

    CPC分类号： G06T15/10

    摘要： A system for mapping texture data at high speed with flexibility to different applications wherein texture data is sent to a memory interface (MEMIF) thorough a digital differential analyzer (DDA) and a texture mapping unit (TMAP) and loaded to free areas of a Z coordinatory memory (ZBUF) and a drawing data memory (FBUF). A Z coordinate value or drawing data is read/written through a bidirectional port. The TMAP converts texture coordinates into a physical address, reads texture data from dedicated read ports of the ZBUF and the FBUF with the physical address, and maps the texture data. Each of the ZBUF and the FBUF has a DRAM unit and an auxiliary memory. Data of one row of the DRAM unit can be sent to the auxiliary memory means at a time. When desired texture data is not present in the auxiliary memory, data of the entire row of the desired texture data is sent to the auxiliary memory and then read.

    摘要翻译： 一种用于将纹理数据高速映射到不同应用的系统，其中纹理数据通过数字差分分析器（DDA）和纹理映射单元（TMAP）发送到存储器接口（MEMIF），并被加载到Z的空闲区域 协调记忆体（ZBUF）和图形数据存储器（FBUF）。 通过双向端口读/写Z坐标值或绘图数据。 TMAP将纹理坐标转换为物理地址，从物理地址的ZBUF和FBUF的专用读取端口读取纹理数据，并映射纹理数据。 每个ZBUF和FBUF都有一个DRAM单元和一个辅助存储器。 DRAM单元的一行的数据可以一次发送到辅助存储装置。 当期望的纹理数据不存在于辅助存储器中时，期望纹理数据的整行的数据被发送到辅助存储器然后读取。

    Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array
    8.
    发明授权
    Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array 失效
    用于在存储器阵列上启用时钟同步读 - 修改 - 写操作的方法和电路

    公开(公告)号：US5996052A

    公开(公告)日：1999-11-30

    申请号：US905565

    申请日：1997-08-04

    申请人： Kazuo Taniguchi ,  Masaharu Yoshimori

    发明人： Kazuo Taniguchi ,  Masaharu Yoshimori

    IPC分类号： G11C11/401 ,  G06T15/00 ,  G09G5/39 ,  G11C7/10 ,  G11C8/18 ,  G11C11/407 ,  G06F12/06

    CPC分类号： G11C7/1072 ,  G11C8/18

    摘要： A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplished in a pipeline manner by the basic synchronized pulse.

    摘要翻译： 一种能够进行数据读取修改写入操作的半导体存储器，包括：存储单元阵列，包括以矩阵形式布置并能够写入和读出数据的多个存储器单元; 读地址解码装置，用于响应于读地址独立地解码读存储单元的地址; 写地址解码装置，用于响应于写地址独立地解码写存储单元的地址; 数据读取装置，用于读取由读取地址解码装置寻址的存储单元的数据; 数据写入装置，用于将数据写入由写入地址解码装置寻址的存储单元; 以及地址延迟装置，由写地址解码装置解码的写地址从读地址解码装置解码的读地址延迟预定时间，其中预定时间被设置为预定的多次基本同步 脉冲周期，使得数据读取修改写入操作以流水线方式通过基本同步脉冲来实现。

    Semiconductor memory device having auxiliary memory
    9.
    发明授权
    Semiconductor memory device having auxiliary memory 失效
    半导体存储器件具有辅助存储器

    公开(公告)号：US5818765A

    公开(公告)日：1998-10-06

    申请号：US912373

    申请日：1997-08-18

    申请人： Kazuo Taniguchi ,  Masayuki Miyabayashi ,  Yuji Yamaguchi

    发明人： Kazuo Taniguchi ,  Masayuki Miyabayashi ,  Yuji Yamaguchi

    IPC分类号： G11C11/401 ,  G06F12/08 ,  G11C7/10 ,  G11C11/00 ,  G11C29/36 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/005 ,  G11C7/103 ,  G11C29/36

    摘要： A semiconductor memory comprising a memory cell array including a plurality of the memory cells arranged in a matrix, the memory cells being able to be written with and read out data; a reading/writing means for reading and writing data with respect to a selected memory cell; a plurality of auxiliary data storing means arranged in series, a first means among them being connected to the memory cell array and each of the auxiliary data storing means storing a part of the data stored in the memory cell array; a plurality of data output means, each of the data output means being connected to one of the auxiliary data storing means; and a plurality of external data buses, each of the external data buses being connected to one of the data output means; each of the data output means being able to independently output the data stored in a corresponding auxiliary data storing means to a corresponding external data bus.

    摘要翻译： 一种半导体存储器，包括存储单元阵列，该存储单元阵列包括以矩阵形式布置的多个存储单元，所述存储单元能够被写入并读出数据; 用于对所选存储单元读取和写入数据的读/写装置; 多个辅助数据存储装置串联布置，其中的第一装置连接到存储单元阵列，并且每个辅助数据存储装置存储存储在存储单元阵列中的数据的一部分; 多个数据输出装置，每个数据输出装置连接到一个辅助数据存储装置; 和多个外部数据总线，每个所述外部数据总线连接到所述数据输出装置之一; 每个数据输出装置能够独立地将存储在相应的辅助数据存储装置中的数据输出到对应的外部数据总线。

    Shared memory device
    10.
    发明申请
    Shared memory device 失效

    公开(公告)号：US20060179256A1

    公开(公告)日：2006-08-10

    申请号：US11344080

    申请日：2006-02-01

    申请人： Goragot Wongpaisarnsin ,  Kazuo Taniguchi ,  Masayuki Miyabayashi

    发明人： Goragot Wongpaisarnsin ,  Kazuo Taniguchi ,  Masayuki Miyabayashi

    IPC分类号： G06F13/28

    CPC分类号： G06F15/167

    摘要： A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and memory macro and transfers information with a memory control unit of a different memory system; the memory macro of each of the memory systems has a memory interface capable of transferring data; and the memory interfaces of the memory macros of different memory systems are mutually connected.