公开(公告)号：US20120013003A1

公开(公告)日：2012-01-19

申请号：US13244395

申请日：2011-09-24

申请人： KENNETH R. RHYNER ,  KEVIN LYNE ,  DAVID G. WONTOR ,  PETER R. HARPER

发明人： KENNETH R. RHYNER ,  KEVIN LYNE ,  DAVID G. WONTOR ,  PETER R. HARPER

IPC分类号： H01L23/485

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor flip-chip ball grid array package with one-metal-layered substrate. The sites of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area, when the sites can be routed for metal plating. The space to place a maximum number of signal routing traces is opened up by interrupting the periodicity of the site array from the edge of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.

摘要翻译： 一种具有单金属层状衬底的半导体倒装芯片球栅阵列封装。 二维阵列的位置可用于将信号（非共同网络分配）I / O类型的焊球附接到芯片区域下方的基板，当该位置可以布线用于金属电镀时。 放置最大数量的信号布线迹线的空间是通过从基片的边缘朝芯片下方的中心中断场址阵列的周期性来打开的。 周期性优选地通过减少二维阵列的整个对齐线和行的中断。

公开(公告)号：US20090289362A1

公开(公告)日：2009-11-26

申请号：US12124292

申请日：2008-05-21

申请人： Kenneth R. Rhyner ,  Peter R. Harper

发明人： Kenneth R. Rhyner ,  Peter R. Harper

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49866 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L24/17 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A high-frequency BGA device (500) with the chip (501) assembled by metal bumps (503) on an insulating substrate (502) with conductive vias (505) and metal traces (504). Chip bumps which serve the high frequency signal terminals are attached directly to the lands (510) on the vias in order to minimize parasitic electrical parameters such as inductance, resistance, and IR drops, thus achieving the required 0.1 nH inductance for each chip terminal. Chip bumps which serve the remaining chip terminals are attached to pads on certain substrate traces. In both cases, the bumps can be attached reliably because the lands on the vias and the pads on the traces are plated with additional metal layers (511, 512), which provide extra thickness as well as a metallurgically suitable surface.

摘要翻译： 具有通过金属凸块（503）在具有导电通孔（505）和金属迹线（504）的绝缘基板（502）上组装的芯片（501）的高频BGA器件（500）。 用于高频信号端子的芯片凸块直接连接到通孔上的焊盘（510）上，以便最小化诸如电感，电阻和IR下降的寄生电参数，从而实现每个芯片端子所需的0.1nH电感。 用于剩余芯片端子的芯片凸块连接到某些衬底迹线上的焊盘。 在这两种情况下，凸起可以可靠地附接，因为通路上的焊盘和迹线上的焊盘镀有额外的金属层（511,512），其提供额外的厚度以及冶金合适的表面。

公开(公告)号：US20090115072A1

公开(公告)日：2009-05-07

申请号：US12124305

申请日：2008-05-21

申请人： KENNETH R. RHYNER ,  KEVIN LYNE ,  DAVID G. WONTOR ,  PETER R. HARPER

发明人： KENNETH R. RHYNER ,  KEVIN LYNE ,  DAVID G. WONTOR ,  PETER R. HARPER

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.

摘要翻译： 一种具有单金属层状基板的半导体倒装芯片球栅阵列封装（600）。 二维阵列的位置（611）可用于将信号（非共同网络分配）I / O类型的焊球附接到芯片区域（601）下方的基板，当位置可以路由为金属 电镀（620）。 通过从基板的边缘（602）朝向芯片下方的中心中断现场阵列的周期性来放置放置最大数量（614）的信号路由迹线的空间。 周期性优选地通过减少二维阵列的整个对齐线和行的中断。

公开(公告)号：US08053349B2

公开(公告)日：2011-11-08

申请号：US12124305

申请日：2008-05-21

申请人： Kenneth R. Rhyner ,  Kevin Lyne ,  David G. Wontor ,  Peter R. Harper

发明人： Kenneth R. Rhyner ,  Kevin Lyne ,  David G. Wontor ,  Peter R. Harper

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.

摘要翻译： 一种具有单金属层状基板的半导体倒装芯片球栅阵列封装（600）。 二维阵列的位置（611）可用于将信号（非共同网络分配）I / O类型的焊球附接到芯片区域（601）下方的基板，当位置可以路由为金属 电镀（620）。 通过从基板的边缘（602）朝向芯片下方的中心中断现场阵列的周期性来放置放置最大数量（614）的信号路由迹线的空间。 周期性优选地通过减少二维阵列的整个对齐线和行的中断。

公开(公告)号：US08674505B2

公开(公告)日：2014-03-18

申请号：US13343880

申请日：2012-01-05

申请人： Kenneth R. Rhyner ,  Peter Harper

发明人： Kenneth R. Rhyner ,  Peter Harper

IPC分类号： H05K1/02

CPC分类号： H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2924/014

摘要： A ball grid array (BGA) includes a plurality of metal balls adapted for connection between an electrical circuit and a substrate. A first portion of the BGA contains a first group of the metal balls arranged according to a first pitch. A second portion of the BGA contains a second group of metal the balls arranged according to a second pitch that is less than the first pitch, to provide increased metal contact area and correspondingly enhanced thermal transfer capability.

摘要翻译： 球栅阵列（BGA）包括适于连接电路和基板的多个金属球。 BGA的第一部分包含根据第一间距布置的第一组金属球。 BGA的第二部分包含第二组金属，根据小于第一节距的第二节距布置球，以提供增加的金属接触面积和相应增强的热传递能力。

公开(公告)号：US20100006987A1

公开(公告)日：2010-01-14

申请号：US12169908

申请日：2008-07-09

申请人： Rajen Murugan ,  Kenneth R. Rhyner ,  Peter R. Harper ,  Souvik Mukherjee

发明人： Rajen Murugan ,  Kenneth R. Rhyner ,  Peter R. Harper ,  Souvik Mukherjee

IPC分类号： H01L23/552 ,  G06F17/50

CPC分类号： H01L23/552 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit (IC) device (200) includes an electronic substrate (201) having a plurality of layers (120) including at least one first electrically conductive layer and a lower surface dielectric layer. The IC device also includes an electrically conductive surface layer (126) disposed on the dielectric layer and coupled to a ground terminal (210) for the electronic substrate (201) for blocking electromagnetic interference (EMI). In the IC device, the conductive surface layer (126) includes an EMI shield region (204) over at least a portion of the dielectric layer. The EMI shield region (204) includes at least one solid area (206) and one or more adhesion areas (207) having a plurality of openings (208) arranged aperiodically in the adhesion areas (207).

摘要翻译： 集成电路（IC）装置（200）包括具有包括至少一个第一导电层和下表面电介质层的多个层（120）的电子基板（201）。 IC器件还包括设置在电介质层上并耦合到用于电子衬底（201）的用于阻挡电磁干扰（EMI）的接地端子（210）的导电表面层（126）。 在IC器件中，导电表面层（126）在电介质层的至少一部分上包括EMI屏蔽区域（204）。 EMI屏蔽区域（204）包括至少一个固体区域（206）和一个或多个粘附区域（207），其具有在粘附区域（207）中非周期地布置的多个开口（208）。

公开(公告)号：US20130175684A1

公开(公告)日：2013-07-11

申请号：US13343880

申请日：2012-01-05

申请人： Kenneth R. Rhyner ,  Peter Harper

发明人： Kenneth R. Rhyner ,  Peter Harper

IPC分类号： H05K1/02 ,  H01L23/488

CPC分类号： H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2924/014

摘要： A ball grid array (BGA) includes a plurality of metal balls adapted for connection between an electrical circuit and a substrate. A first portion of the BGA contains a first group of the metal balls arranged according to a first pitch. A second portion of the BGA contains a second group of metal the balls arranged according to a second pitch that is less than the first pitch, to provide increased metal contact area and correspondingly enhanced thermal transfer capability.

摘要翻译： 球栅阵列（BGA）包括适于连接电路和基板的多个金属球。 BGA的第一部分包含根据第一间距布置的第一组金属球。 BGA的第二部分包含第二组金属，根据小于第一节距的第二节距布置球，以提供增加的金属接触面积和相应增强的热传递能力。