公开(公告)号：US08472762B2

公开(公告)日：2013-06-25

申请号：US12981760

申请日：2010-12-30

申请人： Kyu-Dong Jung ,  Ki-Hun Jeong ,  Dong-Min Keum

发明人： Kyu-Dong Jung ,  Ki-Hun Jeong ,  Dong-Min Keum

IPC分类号： G02B6/32 ,  G02B6/12 ,  G02B6/34

CPC分类号： G02B6/06 ,  G01S3/783

摘要： Provided is an optical sensor and an optical sensor fabricating method. The optical sensor includes: a substrate; and an ommatidia located on or inside the substrate, the ommatidia comprising a microlens which receives light, an optical waveguide which transfers the light received through the microlens, and a cone structure comprising a first end connected to the microlens and a second end connected to the optical waveguide, the cone structure having a diameter or a width decreasing in a direction from the first end to the second end.

摘要翻译： 提供了一种光学传感器和光学传感器制造方法。 光学传感器包括：基板; 以及位于所述基底上或内部的小眼像素，所述眼病包括接收光的微透镜，传送通过所述微透镜接收的光的光波导，以及包括连接到所述微透镜的第一端的锥形结构，以及连接到所述微透镜的第二端 光波导，锥形结构具有在从第一端到第二端的方向上减小的直径或宽度。

公开(公告)号：US20120081795A1

公开(公告)日：2012-04-05

申请号：US13035072

申请日：2011-02-25

申请人： Seung-Tae CHOI ,  Min-Seog CHOI ,  Eun-Sung LEE ,  Kyu-Dong JUNG

发明人： Seung-Tae CHOI ,  Min-Seog CHOI ,  Eun-Sung LEE ,  Kyu-Dong JUNG

IPC分类号： G02B3/12

CPC分类号： G02B3/14

摘要： A vari-focal fluidic lens is provided. The fluidic lens includes a frame, an first membrane, a second membrane, and an optical fluid. The frame defines an inner space of the fluidic lens including a driving portion and a lens portion that are connected to each other. The elastic membrane is attached to one side of the frame to cover at least the lens portion. The second membrane is attached to an opposite side of the frame to cover at least the driving portion and is deformable in response to temperature change to vary a volume of the inner space. Optical fluid is contained in the inner space.

摘要翻译： 提供了变焦流体透镜。 流体透镜包括框架，第一膜，第二膜和光学流体。 框架限定了流体透镜的内部空间，其包括彼此连接的驱动部分和透镜部分。 弹性膜附接到框架的一侧以至少覆盖透镜部分。 第二膜附接到框架的相对侧，以至少覆盖驱动部分，并且响应于温度变化而变形，以改变内部空间的体积。 光学流体包含在内部空间中。

公开(公告)号：US20100309368A1

公开(公告)日：2010-12-09

申请号：US12721180

申请日：2010-03-10

申请人： Min-seog CHOI ,  Eun-sung LEE ,  Kyu-dong JUNG

发明人： Min-seog CHOI ,  Eun-sung LEE ,  Kyu-dong JUNG

IPC分类号： H04N5/225 ,  G02B7/02 ,  G02B9/12 ,  G02B13/18

CPC分类号： G02B13/0085 ,  G02B3/0056 ,  G02B13/0035 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L2924/0002 ,  H04N5/2254 ,  H04N5/2257 ,  H01L2924/00

摘要： Provided are a wafer-level lens module and an image pickup module including the same. The wafer lens module includes a plurality wafer-scale lenses. At least one of the plurality of wafer-scale lenses, such as a wafer-scale lens positioned toward an object side, includes a substrate and a glass lens element formed on one side of the substrate. The glass lens element may be a one-sided lens or a double-sided lens. When the glass lens is a double-sided lens, the substrate may have a through hole. The remaining wafer-scale lenses each include a substrate and polymer lens elements made of UV curable polymer and formed on both sides of the substrate. Also, spacers are interposed between the wafer-scale lenses, along the edge portions of the substrates, so as to maintain predetermined intervals between the wafer-scale lenses.

摘要翻译： 提供了一种晶片级透镜模块和包括该晶片级透镜模块的图像拾取模块。 晶片透镜模块包括多个晶片级透镜。 多个晶片级透镜中的至少一个，例如朝向物体侧定位的晶片级透镜，包括形成在基板的一侧上的基板和玻璃透镜元件。 玻璃透镜元件可以是单面透镜或双面透镜。 当玻璃透镜是双面透镜时，基底可以具有通孔。 其余的晶片级透镜各自包括基板和由UV可固化聚合物制成的聚合物透镜元件，并且形成在基板的两侧。 此外，间隔物沿着基板的边缘部分插入在晶片级透镜之间，以便保持晶片级透镜之间的预定间隔。

公开(公告)号：US07615397B2

公开(公告)日：2009-11-10

申请号：US11584486

申请日：2006-10-23

申请人： Seung Wan Lee ,  Woon Bae Kim ,  Kyu Dong Jung ,  Min Seog Choi

发明人： Seung Wan Lee ,  Woon Bae Kim ,  Kyu Dong Jung ,  Min Seog Choi

IPC分类号： H01L21/00

CPC分类号： H01L27/14618 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A method of manufacturing a micro-element package which can reduce a manufacturing cost and improve productivity by simplifying its structure and manufacturing process, and also can make contributions to miniaturization and thinness, and the micro-element package are provided. The method of the micro-element package including: providing a substrate having a micro-element on its top surface and a transparent cover having a groove on its bottom surface; attaching the transparent cover on the substrate, wherein the bottom surface of the transparent cover where the groove is formed faces the micro-element; exposing the groove by selectively eliminating the transparent cover; and dicing the substrate along the exposed groove.

摘要翻译： 通过简化其结构和制造工艺，可以降低制造成本和提高生产率的微元件封装的制造方法，并且还可以对微型化和薄型化做出贡献，并且提供微元件封装。 微元件封装的方法包括：在其顶表面上提供具有微元件的衬底和在其底表面上具有凹槽的透明盖; 将透明盖安装在基板上，其中形成凹槽的透明盖的底表面面向微元件; 通过选择性地去除透明盖露出凹槽; 并且沿着暴露的凹槽切割衬底。

公开(公告)号：US07605404B2

公开(公告)日：2009-10-20

申请号：US11700067

申请日：2007-01-31

申请人： Kyu Dong Jung ,  Woon Bae Kim ,  Min Seog Choi ,  Seung Wan Lee

发明人： Kyu Dong Jung ,  Woon Bae Kim ,  Min Seog Choi ,  Seung Wan Lee

IPC分类号： H01L29/22 ,  H01L29/227 ,  H01L33/00

CPC分类号： H01L27/14618 ,  H01L27/14625 ,  H01L2224/48091 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H01L2924/00014

摘要： An image pickup device includes a sensor substrate having image sensors arranged in its image pickup region in the form of a matrix. An interlayer insulating film layer is formed below a bottom of the sensor substrate. The interlayer insulating film layer includes wiring layers to construct an electric circuit. The wiring layer is electrically connected with the image sensors. A support substrate is attached on a bottom of the interlayer insulating film layer. The support substrate has contact electrodes formed in via holes. A lens layer is formed over the top surface of the sensor substrate to be opposite to the interlayer insulating film layer. A light-transmitting member is formed over the lens layer.

摘要翻译： 图像拾取装置包括具有以矩阵形式布置在其图像拾取区域中的图像传感器的传感器基板。 在传感器基板的底部的下方形成层间绝缘膜层。 层间绝缘膜层包括构成电路的布线层。 布线层与图像传感器电连接。 支撑基板安装在层间绝缘膜层的底部。 支撑基板具有形成在通孔中的接触电极。 在传感器基板的顶表面上形成与层间绝缘膜层相反的透镜层。 在透镜层上形成透光部件。

公开(公告)号：US20070228403A1

公开(公告)日：2007-10-04

申请号：US11585260

申请日：2006-10-24

申请人： Min Seog Choi ,  Seung Wan Lee ,  Woon Bae Kim ,  Kyu Dong Jung

发明人： Min Seog Choi ,  Seung Wan Lee ,  Woon Bae Kim ,  Kyu Dong Jung

IPC分类号： H01L33/00

CPC分类号： H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A micro-element package module which can reduce manufacturing costs and can be advantageous for mass production due to simplifying its structure and manufacturing process, and also can facilitate miniaturization and promote thinness, and a method of manufacturing the micro-element package module. The micro-element package module includes: an element substrate having a micro-element on a top surface of the element substrate; a circuit substrate that is provided around the element substrate; and an element housing that is provided above the element substrate and the circuit substrate, and includes a connecting section for electrically connecting the micro-element and the circuit substrate.

摘要翻译： 一种微元件封装模块，其可以降低制造成本，并且由于简化其结构和制造工艺而可以有利于批量生产，并且还可以促进小型化和促进薄度，以及制造微元件封装模块的方法。 微元件封装模块包括：元件衬底，其在元件衬底的顶表面上具有微元件; 设置在所述元件基板周围的电路基板; 以及设置在元件基板和电路基板上方的元件外壳，并且包括用于电连接微元件和电路基板的连接部。

公开(公告)号：US20070164410A1

公开(公告)日：2007-07-19

申请号：US11491086

申请日：2006-07-24

申请人： Yong-sung Kim ,  Woon-Bae Kim ,  Kyu-dong Jung ,  Chang-seung Lee

发明人： Yong-sung Kim ,  Woon-Bae Kim ,  Kyu-dong Jung ,  Chang-seung Lee

IPC分类号： H01L23/02

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  B81C2203/0118 ,  H01L23/04 ,  H01L2924/01079 ,  H01L2924/16235

摘要： A fabrication method of a wafer level packaging cap for covering a device wafer provided with a device thereon, includes forming an insulating layer on a wafer; removing a predetermined part of the insulating layer and exposing an upper surface of the wafer; forming a cap pad extending from an upper surface and the exposed surface of the wafer; forming a cavity on a lower surface of the wafer corresponding to the cap pad; etching a bottom surface of the cavity and exposing the cap pad which is connected to the wafer through the cavity; and forming metal lines extending from the lower surface of the wafer and the cavity, to electrically connect the cap pad which is exposed through the cavity.

摘要翻译： 一种用于覆盖其上具有器件的器件晶片的晶片级封装帽的制造方法，包括在晶片上形成绝缘层; 去除所述绝缘层的预定部分并暴露所述晶片的上表面; 形成从所述晶片的上表面和所述暴露表面延伸的盖焊盘; 在与所述盖垫对应的所述晶片的下表面上形成空腔; 蚀刻空腔的底表面并暴露通过空腔连接到晶片的盖垫; 以及形成从所述晶片的下表面和所述腔延伸的金属线，以电连接通过所述空腔暴露的所述盖垫。

公开(公告)号：US07172916B2

公开(公告)日：2007-02-06

申请号：US10701552

申请日：2003-11-06

申请人： Kyu-dong Jung ,  Chan-Bong Jun ,  Hyung Choi ,  Seok-jin Kang ,  Seog-woo Hong ,  Seok-whan Chung ,  Moon-chul Lee ,  Eun-sung Lee

发明人： Kyu-dong Jung ,  Chan-Bong Jun ,  Hyung Choi ,  Seok-jin Kang ,  Seog-woo Hong ,  Seok-whan Chung ,  Moon-chul Lee ,  Eun-sung Lee

IPC分类号： H01L21/00

CPC分类号： B81C1/00285

摘要： A method and apparatus for vacuum-mounting at least one micro electro mechanical system (MEMS) on a substrate includes a gas injecting section for injecting an inert gas into a vacuum chamber; a substrate aligning section for aligning a semiconductor substrate and a cover, the cover having a cavity formed therein and a getter attached to an interior surface of the cavity; a bonding section for bonding the semiconductor substrate and the cover together; and a controlling section for controlling the substrate aligning section to align the semiconductor and the cover, for controlling the gas injecting section to inject the inert gas into the vacuum chamber, and for controlling the bonding section to bond the semiconductor substrate and the cover together after the inert gas is injected.

摘要翻译： 用于真空安装至少一个微机电系统（MEMS）在基板上的方法和装置包括用于将惰性气体注入真空室的气体注入部分; 用于对准半导体衬底和盖的衬底对准部分，所述盖具有形成在其中的空腔和附着到腔的内表面的吸气剂; 用于将半导体衬底和盖结合在一起的接合部分; 以及控制部分，用于控制衬底对准部分以对准半导体和盖子，用于控制气体注入部分以将惰性气体注入真空室中，并且用于控制接合部分将半导体衬底和盖子结合在一起，之后 注入惰性气体。

公开(公告)号：US20060273444A1

公开(公告)日：2006-12-07

申请号：US11390220

申请日：2006-03-28

申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

IPC分类号： H01L23/48

CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

公开(公告)号：US06719918B2

公开(公告)日：2004-04-13

申请号：US10025798

申请日：2001-12-26

申请人： Byeung-leul Lee ,  Taek-ryong Chung ,  Joon-hyock Choi ,  Won-youl Choi ,  Kyu-dong Jung ,  Sang-woo Lee

发明人： Byeung-leul Lee ,  Taek-ryong Chung ,  Joon-hyock Choi ,  Won-youl Choi ,  Kyu-dong Jung ,  Sang-woo Lee

IPC分类号： H01L213065

CPC分类号： H01L21/32137 ,  H01L21/28114

摘要： A method of reducing notching during reactive ion etching (RIE) is provided. The method is useful when RIE is performed to pass through a silicon layer on a multi-layered structure on which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited. The method includes the steps of: forming an insulating layer on a silicon substrate; forming trenches on the insulating layer to expose the silicon substrate; forming a silicon layer on the insulating layer to fill the trenches; and patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches. According to the method, it is possible to remarkably reduce notching without depositing a metal layer, when a multi-layered structure including a silicon layer which is etched to be passed through during RIE is fabricated.

摘要翻译： 提供了一种在反应离子蚀刻（RIE）下减少切口的方法。 当RIE被执行以通过其上依次沉积硅层，绝缘层和硅衬底的多层结构上的硅层时，该方法是有用的。 该方法包括以下步骤：在硅衬底上形成绝缘层; 在绝缘层上形成沟槽以暴露硅衬底; 在所述绝缘层上形成硅层以填充所述沟槽; 以及图案化硅层以形成通过硅层的包括沟槽的第一蚀刻区域。 根据该方法，制造在RIE中被蚀刻而被通过的包含硅层的多层结构时，不沉积金属层可显着地减少切口。