公开(公告)号：US06719918B2

公开(公告)日：2004-04-13

申请号：US10025798

申请日：2001-12-26

申请人： Byeung-leul Lee ,  Taek-ryong Chung ,  Joon-hyock Choi ,  Won-youl Choi ,  Kyu-dong Jung ,  Sang-woo Lee

发明人： Byeung-leul Lee ,  Taek-ryong Chung ,  Joon-hyock Choi ,  Won-youl Choi ,  Kyu-dong Jung ,  Sang-woo Lee

IPC分类号： H01L213065

CPC分类号： H01L21/32137 ,  H01L21/28114

摘要： A method of reducing notching during reactive ion etching (RIE) is provided. The method is useful when RIE is performed to pass through a silicon layer on a multi-layered structure on which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited. The method includes the steps of: forming an insulating layer on a silicon substrate; forming trenches on the insulating layer to expose the silicon substrate; forming a silicon layer on the insulating layer to fill the trenches; and patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches. According to the method, it is possible to remarkably reduce notching without depositing a metal layer, when a multi-layered structure including a silicon layer which is etched to be passed through during RIE is fabricated.

摘要翻译： 提供了一种在反应离子蚀刻（RIE）下减少切口的方法。 当RIE被执行以通过其上依次沉积硅层，绝缘层和硅衬底的多层结构上的硅层时，该方法是有用的。 该方法包括以下步骤：在硅衬底上形成绝缘层; 在绝缘层上形成沟槽以暴露硅衬底; 在所述绝缘层上形成硅层以填充所述沟槽; 以及图案化硅层以形成通过硅层的包括沟槽的第一蚀刻区域。 根据该方法，制造在RIE中被蚀刻而被通过的包含硅层的多层结构时，不沉积金属层可显着地减少切口。

公开(公告)号：US06739189B2

公开(公告)日：2004-05-25

申请号：US10121666

申请日：2002-04-15

申请人： Byeung-leul Lee ,  Kyu-dong Jung ,  Sang-woo Lee ,  Yong-chul Cho

发明人： Byeung-leul Lee ,  Kyu-dong Jung ,  Sang-woo Lee ,  Yong-chul Cho

IPC分类号： G01P1500

CPC分类号： G01P15/18 ,  B81B2203/0136 ,  B81C1/0015 ,  B81C2201/0132 ,  G01C19/5755 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0831

摘要： Provided are a structure for detecting a vertical displacement and its manufacturing method. The structure for detecting a vertical displacement includes a body, an inertial mass floated over the body, a plurality of support beams extending from the inertial mass so as to suspend the inertial mass over the body, movable electrodes integrally formed with the inertial mass, and fixed electrodes floated over the body, each being positioned between the neighboring movable electrodes, wherein a vertical length of the movable electrode is different from a vertical length of the fixed electrode. Therefore, the structure and the electrodes can be simultaneously manufactured, thereby making the fabrication process simple. Also, it is possible to manufacture a three-axis accelerometer and a three-axis gyroscope on a single wafer by the same process, to be integrated as a six-axis inertial sensor.

摘要翻译： 提供了用于检测垂直位移的结构及其制造方法。 用于检测垂直位移的结构包括主体，悬挂在主体上的惯性质量，从惯性块延伸的多个支撑梁，以将惯性块悬挂在主体上，与惯性块一体形成的可动电极，以及 固定电极浮在身体上，每个固定电极位于相邻的可移动电极之间，其中可移动电极的垂直长度不同于固定电极的垂直长度。 因此，可以同时制造结构和电极，从而使制造工艺简单。 另外，可以通过相同的工艺在单个晶片上制造三轴加速度计和三轴陀螺仪，作为六轴惯性传感器集成。

公开(公告)号：US20070164410A1

公开(公告)日：2007-07-19

申请号：US11491086

申请日：2006-07-24

申请人： Yong-sung Kim ,  Woon-Bae Kim ,  Kyu-dong Jung ,  Chang-seung Lee

发明人： Yong-sung Kim ,  Woon-Bae Kim ,  Kyu-dong Jung ,  Chang-seung Lee

IPC分类号： H01L23/02

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  B81C2203/0118 ,  H01L23/04 ,  H01L2924/01079 ,  H01L2924/16235

摘要： A fabrication method of a wafer level packaging cap for covering a device wafer provided with a device thereon, includes forming an insulating layer on a wafer; removing a predetermined part of the insulating layer and exposing an upper surface of the wafer; forming a cap pad extending from an upper surface and the exposed surface of the wafer; forming a cavity on a lower surface of the wafer corresponding to the cap pad; etching a bottom surface of the cavity and exposing the cap pad which is connected to the wafer through the cavity; and forming metal lines extending from the lower surface of the wafer and the cavity, to electrically connect the cap pad which is exposed through the cavity.

摘要翻译： 一种用于覆盖其上具有器件的器件晶片的晶片级封装帽的制造方法，包括在晶片上形成绝缘层; 去除所述绝缘层的预定部分并暴露所述晶片的上表面; 形成从所述晶片的上表面和所述暴露表面延伸的盖焊盘; 在与所述盖垫对应的所述晶片的下表面上形成空腔; 蚀刻空腔的底表面并暴露通过空腔连接到晶片的盖垫; 以及形成从所述晶片的下表面和所述腔延伸的金属线，以电连接通过所述空腔暴露的所述盖垫。

公开(公告)号：US07172916B2

公开(公告)日：2007-02-06

申请号：US10701552

申请日：2003-11-06

申请人： Kyu-dong Jung ,  Chan-Bong Jun ,  Hyung Choi ,  Seok-jin Kang ,  Seog-woo Hong ,  Seok-whan Chung ,  Moon-chul Lee ,  Eun-sung Lee

发明人： Kyu-dong Jung ,  Chan-Bong Jun ,  Hyung Choi ,  Seok-jin Kang ,  Seog-woo Hong ,  Seok-whan Chung ,  Moon-chul Lee ,  Eun-sung Lee

IPC分类号： H01L21/00

CPC分类号： B81C1/00285

摘要： A method and apparatus for vacuum-mounting at least one micro electro mechanical system (MEMS) on a substrate includes a gas injecting section for injecting an inert gas into a vacuum chamber; a substrate aligning section for aligning a semiconductor substrate and a cover, the cover having a cavity formed therein and a getter attached to an interior surface of the cavity; a bonding section for bonding the semiconductor substrate and the cover together; and a controlling section for controlling the substrate aligning section to align the semiconductor and the cover, for controlling the gas injecting section to inject the inert gas into the vacuum chamber, and for controlling the bonding section to bond the semiconductor substrate and the cover together after the inert gas is injected.

摘要翻译： 用于真空安装至少一个微机电系统（MEMS）在基板上的方法和装置包括用于将惰性气体注入真空室的气体注入部分; 用于对准半导体衬底和盖的衬底对准部分，所述盖具有形成在其中的空腔和附着到腔的内表面的吸气剂; 用于将半导体衬底和盖结合在一起的接合部分; 以及控制部分，用于控制衬底对准部分以对准半导体和盖子，用于控制气体注入部分以将惰性气体注入真空室中，并且用于控制接合部分将半导体衬底和盖子结合在一起，之后 注入惰性气体。

公开(公告)号：US20060273444A1

公开(公告)日：2006-12-07

申请号：US11390220

申请日：2006-03-28

申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

IPC分类号： H01L23/48

CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

公开(公告)号：US09629552B2

公开(公告)日：2017-04-25

申请号：US13615048

申请日：2012-09-13

申请人： Min-seog Choi ,  Seung-wan Lee ,  Woon-bae Kim ,  Eun-sung Lee ,  Kyu-dong Jung ,  Jong-hyeon Chang

发明人： Min-seog Choi ,  Seung-wan Lee ,  Woon-bae Kim ,  Eun-sung Lee ,  Kyu-dong Jung ,  Jong-hyeon Chang

IPC分类号： A61B5/05 ,  A61B5/00 ,  G01B9/02 ,  G02B5/00 ,  G02B21/00 ,  G02B26/00 ,  G02B26/10 ,  G01B11/22 ,  G02B3/14

CPC分类号： A61B5/0066 ,  A61B5/444 ,  G01B9/02063 ,  G01B9/02091 ,  G01B11/22 ,  G02B3/14 ,  G02B5/005 ,  G02B21/006 ,  G02B26/005 ,  G02B26/101

摘要： A numerical aperture (NA) controlling unit and a variable optical probe including the same are provided. The NA controlling unit includes: an aperture adjustment unit which controls an aperture through which light is transmitted; and a focus control unit that is disposed in a predetermined position with respect to the aperture adjustment unit, that focuses light transmitted through the aperture, and that has an adjustable focal length. The variable optical probe includes: a light transmission unit; a collimator that collimates light transmitted through the light transmission unit into parallel light; an NA controlling unit that focuses light on a sample to be inspected; and a scanner that varies a path of light transmitted through the light transmission unit such that a predetermined region of the sample is scanned by light that passes through the NA controlling unit.

公开(公告)号：US09188774B2

公开(公告)日：2015-11-17

申请号：US13616572

申请日：2012-09-14

申请人： Kyu-dong Jung ,  Jong-hyeon Chang ,  Min-seog Choi

发明人： Kyu-dong Jung ,  Jong-hyeon Chang ,  Min-seog Choi

IPC分类号： G02B26/02

CPC分类号： G02B26/02 ,  G02B2207/115

摘要： A microelectrofluidic device includes: a chamber; a first fluid and a second fluid which are contained in the chamber and are not mixable with each other; and a first electrode group including a plurality of electrodes that are disposed on an inner side of the chamber, and to which a voltage is applied to change an interface between the first fluid and the second fluid, wherein the plurality of electrodes are connected to form a first electrode unit, a second electrode unit, and a third electrode unit that are independently turned on or off, and the plurality of electrodes are annular and coated with an insulating material, and adjacent electrodes are connected to different electrode units.

摘要翻译： 微电流流体装置包括：腔室; 第一流体和第二流体，其容纳在所述室中并且不能彼此混合; 以及第一电极组，其包括设置在所述室的内侧的多个电极，并且施加电压以改变所述第一流体和所述第二流体之间的界面，其中所述多个电极连接形成 独立地接通或断开的第一电极单元，第二电极单元和第三电极单元，并且多个电极是环形的并且涂覆有绝缘材料，并且相邻的电极连接到不同的电极单元。

公开(公告)号：US20070008050A1

公开(公告)日：2007-01-11

申请号：US11397704

申请日：2006-04-05

申请人： Kyu-dong Jung ,  Jong-oh Kwon ,  Woon-bae Kim ,  In-sang Song

发明人： Kyu-dong Jung ,  Jong-oh Kwon ,  Woon-bae Kim ,  In-sang Song

IPC分类号： H03H9/54

CPC分类号： H03H9/173 ,  H03H3/02 ,  H03H9/174 ,  H03H2003/021 ,  H03H2003/023

摘要： A bulk acoustic resonance and a method for fabricating the bulk acoustic resonator, the bulk acoustic resonator including: a substrate including an upper surface defining a predetermined area including a cavity; a resonance part positioned above the cavity and including a surface comprising a dimple; and an anchor part connecting the resonance part to the substrate. The resonance part includes: a lower electrode including a lower surface including a predetermined dimpled area and an upper surface opposite to the predetermined dimpled area; a piezoelectric layer stacked on the upper surface of the lower electrode; and an upper electrode stacked on the piezoelectric layer. Because direction of the vibration of the resonator is adjustable by adjusting position, area, and the number of the dimples, process freedom can be improved.

摘要翻译： 一种体声共振和一种用于制造体声波谐振器的方法，所述体声波谐振器包括：基板，包括限定包括空腔的预定区域的上表面; 谐振部分，其位于空腔上方并包括包括凹坑的表面; 以及将共振部分连接到基板的锚固部分。 共振部包括：下电极，其包括具有预定凹坑区域的下表面和与预定凹坑区域相对的上表面; 压电层，堆叠在下电极的上表面上; 以及堆叠在压电层上的上电极。 由于通过调节位置，面积和凹坑的数量来调节谐振器的振动方向，可以提高工艺自由度。

公开(公告)号：US20060255443A1

公开(公告)日：2006-11-16

申请号：US11391211

申请日：2006-03-29

申请人： Jun-sik Hwang ,  Woon-bae Kim ,  Chang-youl Moon ,  Moon-chul Lee ,  Kyu-dong Jung

发明人： Jun-sik Hwang ,  Woon-bae Kim ,  Chang-youl Moon ,  Moon-chul Lee ,  Kyu-dong Jung

IPC分类号： H01L23/02

CPC分类号： B81C1/0023 ,  B81B7/007 ,  B81C2203/0118 ,  H01L23/04 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48463 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.

摘要翻译： 提供了一种多层封装芯片及其制造方法。 该方法包括在第一晶片上形成至少一个第二电路元件; 形成具有空腔的第二晶片和与所述腔相对形成的一个第三电路元件; 在第二晶片上形成焊料; 以及将所述第二晶片与所述第一晶片组合以使得所述第二电路元件和所述空腔对应。 芯片包括倒装芯片封装芯片，其中使用第一晶片封装第一电路元件; 形成在第一晶片上的第二电路元件; 第二晶片，其具有空腔并与所述第一晶片组合，使得所述空腔和所述第二电路元件对应; 形成在第二晶片上的第三电路元件; 以及形成在所述第二晶片上的焊料，所述焊料将所述第二晶片电耦合到封装衬底。

公开(公告)号：US06952965B2

公开(公告)日：2005-10-11

申请号：US10744099

申请日：2003-12-24

申请人： Seok-jin Kang ,  Seok-whan Chung ,  Moon-chul Lee ,  Kyu-dong Jung ,  Seog-soo Hong

发明人： Seok-jin Kang ,  Seok-whan Chung ,  Moon-chul Lee ,  Kyu-dong Jung ,  Seog-soo Hong

IPC分类号： B81B7/00 ,  B81B3/00 ,  B81B5/00 ,  B81C1/00 ,  G01C19/56 ,  G01C19/5762 ,  G01C19/5769 ,  G01P9/04

CPC分类号： G01C19/5762 ,  B81B3/0059 ,  B81B2201/0242 ,  B81B2203/051 ,  B81B2203/053

摘要： A vertical MEMS gyroscope by horizontal driving includes a substrate, a support layer fixed on an upper surface of an area of the substrate, a driving structure floating above the substrate and having a portion fixed to an upper surface of the support layer and another portion in parallel with the fixed portion, the driving structure having a predetermined area capable of vibrating in a predetermined direction parallel to the substrate, a detecting structure fixed to the driving structure on a same plane as the driving structure, and having a predetermined area capable of vibrating in a vertical direction with respect to the substrate, a cap wafer bonded with the substrate positioned above the driving structure and the detecting structure, and a fixed vertical displacement detection electrode formed at a predetermined location of an underside of the cap wafer, for detecting displacement of the detecting structure in the vertical direction.

摘要翻译： 通过水平驱动的垂直MEMS陀螺仪包括基板，固定在基板的区域的上表面上的支撑层，浮动在基板上方并具有固定到支撑层的上表面的部分的驱动结构， 平行于固定部分，驱动结构具有能够在与基板平行的预定方向上振动的预定区域;检测结构，其在与驱动结构相同的平面上固定到驱动结构，并且具有能够振动的预定区域 在相对于基板的垂直方向上，与位于驱动结构上方的基板接合的盖晶片和检测结构，以及形成在盖晶片的下侧的预定位置处的固定垂直位移检测电极，用于检测位移 的检测结构。