公开(公告)号：US20140273524A1

公开(公告)日：2014-09-18

申请号：US14204490

申请日：2014-03-11

Applicant: Victor Nguyen ,  Mihaela Balseanu ,  Li-Qun Xia ,  Ning Li ,  Martin A. Hilkene ,  Matthew D. Scotney-Castle

Inventor： Victor Nguyen ,  Mihaela Balseanu ,  Li-Qun Xia ,  Ning Li ,  Martin A. Hilkene ,  Matthew D. Scotney-Castle

IPC: H01L21/02

CPC classification number: H01L21/02321 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/31155

Abstract: Provided are methods for the deposition and doping of films comprising Si. Certain methods involve depositing a SiN, SiO, SiON, SiC or SiCN film and doping the Si-containing film with one or more of C, B, O, N and Ge by a plasma implantation process. Such doped Si-containing films may have improved properties such as reduced etch rate in acid-based clean solutions, reduced dielectric constant and/or improved dielectric strength.

Abstract translation: 提供了用于沉积和掺杂包含Si的膜的方法。 某些方法包括沉积SiN，SiO，SiON，SiC或SiCN膜，并通过等离子体注入工艺将C，B，O，N和Ge中的一种或多种掺杂到含Si薄膜。 这种掺杂的含Si薄膜可具有改进的性能，例如在酸基清洁溶液中降低的蚀刻速率，降低的介电常数和/或改善的介电强度。

公开(公告)号：US08501568B2

公开(公告)日：2013-08-06

申请号：US12256173

申请日：2008-10-22

Applicant: Mihaela Balseanu ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

Inventor： Mihaela Balseanu ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

IPC: H01L21/326 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/00 ,  H01L29/792

CPC classification number: H01L21/3185 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792

Abstract: A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

Abstract translation: 提供了形成闪速存储器件的方法。 闪存器件包括在衬底上的二氧化硅层和形成在二氧化硅层上的氮化硅层。 氮化硅层的性质可以通过以下任何方式改变：将氮化硅层暴露于紫外线辐射，将氮化硅层暴露于电子束，以及通过等离子体处理氮化硅层。 介电材料沉积在氮化硅层上，并且在电介质材料上形成导电日期。 具有改进的氮化硅层的闪速存储器件提供了非易失性存储器件的单元电池的电荷保持容量和电荷保持时间的增加。

公开(公告)号：US20130005146A1

公开(公告)日：2013-01-03

申请号：US13612159

申请日：2012-09-12

Applicant: Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son Nguyen ,  Li-Qun Xia

Inventor： Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son Nguyen ,  Li-Qun Xia

IPC: H01L21/285

CPC classification number: B82Y40/00 ,  B82Y30/00 ,  H01L21/02112 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride.

Abstract translation: 本公开提供了一种符合下面的衬底（即互连结构）的多层盖（即迁移屏障）。 可以位于互连结构的至少一个互连级别上方的多层盖包括从底部到顶部包括氮化硅的第一层和包含氮化硼和碳氮化硼中的至少一种的第二层。

公开(公告)号：US20120196452A1

公开(公告)日：2012-08-02

申请号：US13365229

申请日：2012-02-02

Applicant: Mihaela Balseanu ,  Michael S. Cox ,  Li-Qun Xia ,  Mei-Yee Shek ,  Jia Lee ,  Vladimir Zubkov ,  Tzu-Fang Huang ,  Rongping Wang ,  Isabelita Roflox ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Michael S. Cox ,  Li-Qun Xia ,  Mei-Yee Shek ,  Jia Lee ,  Vladimir Zubkov ,  Tzu-Fang Huang ,  Rongping Wang ,  Isabelita Roflox ,  Hichem M'Saad

IPC: H01L21/318

CPC classification number: C23C16/345 ,  C23C16/45523 ,  C23C16/56 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823835

Abstract: High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si—N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400° C., and exposing the deposited silicon nitride film to ultraviolet radiation.

Abstract translation: 沉积层（例如氮化硅层）中的高拉伸应力可以利用单独使用或组合使用的一种或多种技术来实现。 在一个实施例中，可以通过在致孔剂的存在下沉积氮化硅膜来形成具有高拉伸应力的氮化硅膜。 沉积的氮化硅膜可以暴露于选自等离子体或紫外线辐射的至少一种处理以释放致孔剂。 可以使氮化硅膜致密化，使致孔剂释放产生的孔尺寸减小，并且氮化硅膜中的Si-N键变形以在氮化硅膜中产生拉伸应力。 在另一个实施例中，可以通过在低于约400℃的温度下在含氮等离子体的存在下沉积氮化硅膜来增强氮化硅膜中的拉伸应力，并将沉积的氮化硅膜暴露于紫外线 辐射。

公开(公告)号：US08084105B2

公开(公告)日：2011-12-27

申请号：US11765257

申请日：2007-06-19

Applicant: Jeong-Uk Huh ,  Mihaela Balseanu ,  Li-Qun Xia ,  Victor T. Nguyen ,  Derek R. Witty ,  Hichem M'Saad

Inventor： Jeong-Uk Huh ,  Mihaela Balseanu ,  Li-Qun Xia ,  Victor T. Nguyen ,  Derek R. Witty ,  Hichem M'Saad

IPC: H05H1/24

CPC classification number: C23C16/342 ,  C23C16/45523

Abstract: Methods for forming boron-containing films are provided. The methods include introducing a boron-containing precursor and a nitrogen or oxygen-containing precursor into a chamber and forming a boron nitride or boron oxide film on a substrate in the chamber. In one aspect, the method includes depositing a boron-containing film and then exposing the boron-containing film to the nitrogen-containing or oxygen-containing precursor to incorporate nitrogen or oxygen into the film. The deposition of the boron-containing film and exposure of the film to the precursor may be performed for multiple cycles to obtain a desired thickness of the film. In another aspect, the method includes reacting the boron-containing precursor and the nitrogen-containing or oxygen-containing precursor to chemically vapor deposit the boron nitride or boron oxide film.

Abstract translation: 提供了形成含硼膜的方法。 所述方法包括将含硼前体和含氮或含氧前体引入室中，并在室中的基底上形成氮化硼或氧化硼膜。 一方面，该方法包括沉积含硼膜，然后将含硼膜暴露于含氮或含氧前体以将氮或氧引入膜中。 含硼膜的沉积和膜暴露于前体可以进行多个循环以获得所需的膜厚度。 另一方面，该方法包括使含硼前体和含氮或含氧前体反应以化学气相沉积氮化硼或氧化硼膜。

公开(公告)号：US20100096687A1

公开(公告)日：2010-04-22

申请号：US12255617

申请日：2008-10-21

Applicant: Mihaela BALSEANU ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

Inventor： Mihaela BALSEANU ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

IPC: H01L29/78 ,  H01L21/3205 ,  H01L21/31

CPC classification number: H01L21/3185 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792

Abstract: A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

Abstract translation: 提供闪速存储器件和形成闪存器件的方法。 闪速存储器件包括具有包含碳，硼或氧的掺杂剂的掺杂氮化硅层。 掺杂的氮化硅层在该层中产生更高数量和更高浓度的氮和硅悬挂键，并且提供了非易失性存储器件的单元电池的电荷保持容量和电荷保留时间的增加。

公开(公告)号：US07601651B2

公开(公告)日：2009-10-13

申请号：US11668911

申请日：2007-01-30

Applicant: Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

IPC: H01L21/31

CPC classification number: H01L21/76834 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831

Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.

Abstract translation: 提供了一种在室中的衬底上形成层的方法，其中衬底在其表面上具有至少一个形成的特征。 该方法包括在存在等离子体的情况下将衬底暴露于含硅前体以沉积一层，用等离子体处理沉积层，并重复曝光和处理，直到获得所需层厚。 等离子体可以由含氧气体产生。

公开(公告)号：US07566655B2

公开(公告)日：2009-07-28

申请号：US11398436

申请日：2006-04-05

Applicant: Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC: H01L21/44

CPC classification number: H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

Abstract: A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

Abstract translation: 工艺流程集成方案采用一种或多种技术来控制由此形成的半导体器件中的应力。 根据一个实施例，由氮化物间隔物和多晶硅栅极的RTP贡献的累积应力以及随后沉积高应力蚀刻停止层，增强应变并提高器件性能。 可以将锗沉积或植入栅极结构中以便于应力控制。

公开(公告)号：US20090093112A1

公开(公告)日：2009-04-09

申请号：US11869396

申请日：2007-10-09

Applicant: AMIR AL-BAYATI ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang 'David' Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

Inventor： AMIR AL-BAYATI ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang 'David' Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

Abstract: A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.

Abstract translation: 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。

公开(公告)号：US20080020591A1

公开(公告)日：2008-01-24

申请号：US11762590

申请日：2007-06-13

Applicant: Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

Inventor： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

IPC: H01L21/31

CPC classification number: H01L21/3105 ,  C23C16/345 ,  C23C16/56 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/66583 ,  H01L29/7843

Abstract: Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with alternative embodiments, a deposited silicon nitride film is exposed to curing with ultraviolet (UV) radiation at an elevated temperature, thereby helping remove hydrogen from the film and increasing film stress. In accordance with still other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

Abstract translation: 氮化硅层的应力可以通过在较高温度下沉积来增强。 使用允许将衬底加热到​​基本上大于400℃的装置（例如由陶瓷而不是铝制成的加热器），沉积的氮化硅膜可能表现出增强的应力，从而可以改善下面的MOS晶体管的性能 设备。 根据替代实施例，沉积的氮化硅膜在升高的温度下暴露于紫外线（UV）辐射固化，从而有助于从膜中除去氢并增加膜应力。 根据其他实施例，使用采用多个沉积/固化周期的整合方法形成氮化硅膜，以保持薄膜在底层凸起特征的尖角处的完整性。 可以通过在每个循环中包括UV后固化等离子体处理来促进连续层之间的粘附。