公开(公告)号：US20060046479A1

公开(公告)日：2006-03-02

申请号：US10929884

申请日：2004-08-30

Applicant: Nagarajan Rajagopalan ,  Meiyee Shek ,  Albert Lee ,  Annamalai Lakshmanan ,  Li-Qun Xia ,  Zhenjiang Cui

Inventor： Nagarajan Rajagopalan ,  Meiyee Shek ,  Albert Lee ,  Annamalai Lakshmanan ,  Li-Qun Xia ,  Zhenjiang Cui

IPC: H01L21/44 ,  H01L21/31

CPC classification number: H01L21/02211 ,  C23C16/325 ,  C23C16/36 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed thereon, introducing a reducing compound or a silicon based compound, exposing the conductive material to the reducing compound or the silicon based compound, and depositing a silicon carbide layer without breaking vacuum.

Abstract translation: 提供了用于处理用于在导电材料和电介质层之间沉积粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括定位其上布置有导电材料的衬底，引入还原化合物或硅基化合物，将导电材料暴露于还原化合物或硅基化合物，以及沉积 没有破坏真空的碳化硅层。

公开(公告)号：US20050233555A1

公开(公告)日：2005-10-20

申请号：US10828023

申请日：2004-04-19

Applicant: Nagarajan Rajagopalan ,  Meiyee Shek ,  Albert Lee ,  Annamalai Lakshmanan ,  Li-Qun Xia ,  Zhenjiang Cui

Inventor： Nagarajan Rajagopalan ,  Meiyee Shek ,  Albert Lee ,  Annamalai Lakshmanan ,  Li-Qun Xia ,  Zhenjiang Cui

IPC: B05D3/00 ,  C08J7/18 ,  C23C16/32 ,  C30B1/00 ,  G21H5/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/3115 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/36 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/321 ,  C23C16/325 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/3115 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76886

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed thereon, introducing a reducing compound or a silicon based compound, exposing the conductive material to the reducing compound or the silicon based compound, and depositing a silicon carbide layer without breaking vacuum.

Abstract translation: 提供了用于处理用于在导电材料和电介质层之间沉积粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括定位其上布置有导电材料的衬底，引入还原化合物或硅基化合物，将导电材料暴露于还原化合物或硅基化合物，以及沉积 没有破坏真空的碳化硅层。

公开(公告)号：US20090286402A1

公开(公告)日：2009-11-19

申请号：US12257137

申请日：2008-10-23

Applicant: Li-Qun Xia ,  Mihaela Balseanu ,  Meiyee Shek ,  Siyi Li ,  Zhenjiang Cui ,  Mehul B. Naik ,  Michael D. Armacost ,  William H. McClintock

Inventor： Li-Qun Xia ,  Mihaela Balseanu ,  Meiyee Shek ,  Siyi Li ,  Zhenjiang Cui ,  Mehul B. Naik ,  Michael D. Armacost ,  William H. McClintock

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/02112 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76816

Abstract: A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.

Abstract translation: 提供了一种用于在基板中形成窄通孔的方法和装置。 通过常规光刻将图案凹槽蚀刻到基底中。 在衬底的表面上形成薄的共形层，包括图案凹槽的侧壁和底部。 共形层的厚度减小了图案凹槽的有效宽度。 通过各向异性蚀刻从图案凹槽的底部去除共形层以暴露下面的衬底。 然后使用覆盖图案凹槽的侧壁的保形层作为掩模蚀刻衬底。 然后使用湿蚀刻剂除去保形层。

公开(公告)号：US20090011148A1

公开(公告)日：2009-01-08

申请号：US12214393

申请日：2008-06-17

Applicant: Nagarajan Rajagopalan ,  Bok Heon Kim ,  Lester A. D'Cruz ,  Zhenjiang Cui ,  Girish A. Dixit ,  Visweswaren Sivaramakrishnan ,  Hichem M'Saad ,  Meiyee Shek ,  Li-Qun Xia

Inventor： Nagarajan Rajagopalan ,  Bok Heon Kim ,  Lester A. D'Cruz ,  Zhenjiang Cui ,  Girish A. Dixit ,  Visweswaren Sivaramakrishnan ,  Hichem M'Saad ,  Meiyee Shek ,  Li-Qun Xia

IPC: C23C16/22

CPC classification number: H01L21/76838 ,  C23C16/0272 ,  C23C16/42

Abstract: Adhesion between a copper metallization layer and a dielectric barrier film may be promoted by stabilizing a flow of a silicon-containing precursor in a divert line leading to the chamber exhaust. The stabilized gas flow is then introduced to the processing chamber to precisely form a silicide layer over the copper. This silicidation step creates a network of strong Cu—Si bonds that prevent delamination of the barrier layer, while not substantially altering the sheet resistance and other electrical properties of the resulting metallization structure.

Abstract translation: 铜金属化层和电介质阻挡膜之间的粘附可以通过使通过室排气的转向管中的含硅前体的流动稳定而得到促进。 然后将稳定的气流引入处理室，以在铜上精确地形成硅化物层。 该硅化步骤产生强的Cu-Si键的网络，其防止阻挡层的分层，而基本上不改变所得金属化结构的薄层电阻和其它电性能。

公开(公告)号：US20090269923A1

公开(公告)日：2009-10-29

申请号：US12109533

申请日：2008-04-25

Applicant: Sang M. Lee ,  Yong-Won Lee ,  Meiyee Shek ,  Li-Qun Xia ,  Derek R. Witty

Inventor： Sang M. Lee ,  Yong-Won Lee ,  Meiyee Shek ,  Li-Qun Xia ,  Derek R. Witty

IPC: H01L21/321

CPC classification number: H01L21/02074 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886

Abstract: A method and apparatus for processing a substrate is provided. The method of processing a substrate includes providing a substrate comprising a conductive material, performing a pre-treatment process on the conductive material, flowing a silicon based compound on the conductive material to form a silicide layer, performing a post treatment process on the silicide layer, and depositing a barrier dielectric layer on the substrate.

Abstract translation: 提供了一种用于处理衬底的方法和设备。 处理衬底的方法包括提供包括导电材料的衬底，对导电材料执行预处理工艺，在导电材料上流动硅基化合物以形成硅化物层，对硅化物层进行后处理工艺 ，并在衬底上沉积阻挡介电层。

公开(公告)号：US07601651B2

公开(公告)日：2009-10-13

申请号：US11668911

申请日：2007-01-30

Applicant: Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

IPC: H01L21/31

CPC classification number: H01L21/76834 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831

Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.

Abstract translation: 提供了一种在室中的衬底上形成层的方法，其中衬底在其表面上具有至少一个形成的特征。 该方法包括在存在等离子体的情况下将衬底暴露于含硅前体以沉积一层，用等离子体处理沉积层，并重复曝光和处理，直到获得所需层厚。 等离子体可以由含氧气体产生。

公开(公告)号：US07371427B2

公开(公告)日：2008-05-13

申请号：US10442579

申请日：2003-05-20

Applicant: Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

Inventor： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

IPC: B08B9/00 ,  B05D7/22

CPC classification number: H01L21/7684 ,  C23C16/4404 ,  C23G5/00 ,  H01L21/3212 ,  H01L21/76828 ,  H01L21/76838

Abstract: Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Abstract translation: 由于形成覆盖势垒层而在铜层中产生的不希望的小丘可以通过单独或组合优化各种工艺参数而显着降低。 可以控制第一组工艺参数以对其中沉积阻挡层的处理室进行预处理。 可以控制第二组工艺参数，以在阻挡层沉积之前最小化去除CuO期间铜层暴露的能量。 可以控制第三组工艺参数以最小化除去氧化铜后的热预算。

公开(公告)号：US20080075888A1

公开(公告)日：2008-03-27

申请号：US11876680

申请日：2007-10-22

Applicant: Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Heon Kim ,  Hichem M'saad ,  Thomas Nowak

Inventor： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Heon Kim ,  Hichem M'saad ,  Thomas Nowak

IPC: H05H1/24

CPC classification number: H01L21/7684 ,  C23C16/4404 ,  C23G5/00 ,  H01L21/3212 ,  H01L21/76828 ,  H01L21/76838

Abstract: Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Abstract translation: 由于形成覆盖势垒层而在铜层中产生的不希望的小丘可以通过单独或组合优化各种工艺参数而显着降低。 可以控制第一组工艺参数以对其中沉积阻挡层的处理室进行预处理。 可以控制第二组工艺参数，以在阻挡层沉积之前最小化去除CuO期间铜层暴露的能量。 可以控制第三组工艺参数以最小化除去氧化铜后的热预算。

公开(公告)号：US08236684B2

公开(公告)日：2012-08-07

申请号：US12147986

申请日：2008-06-27

Applicant: Kelvin Chan ,  Khaled A. Elsheref ,  Alexandros T. Demos ,  Meiyee Shek ,  Lipan Li ,  Li-Qun Xia ,  Kang sub Yim

Inventor： Kelvin Chan ,  Khaled A. Elsheref ,  Alexandros T. Demos ,  Meiyee Shek ,  Lipan Li ,  Li-Qun Xia ,  Kang sub Yim

IPC: H01L21/4763

CPC classification number: H01L21/3141 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/76814 ,  H01L21/76831

Abstract: A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.

Abstract translation: 提供了一种处理基板的方法和装置。 在基板上形成多孔介电层。 在一些实施例中，电介质可以由致密的电介质层封盖。 对电介质层进行图案化，并且将致密的电介质层保形地沉积在衬底上。 密实的保形介电层密封多孔介电层的孔隙，防止与可能渗入孔隙的物质接触。 通过定向选择性蚀刻去除覆盖图案开口的场区域和底部部分的致密保形孔隙电介质层的部分。

公开(公告)号：US07723228B2

公开(公告)日：2010-05-25

申请号：US10442359

申请日：2003-05-20

Applicant: Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

Inventor： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

IPC: H01L21/4763

CPC classification number: H01L21/76838 ,  H01L21/02074 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76828 ,  H01L21/7684

Abstract: Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Abstract translation: 由于形成覆盖势垒层而在铜层中产生的不希望的小丘可以通过单独或组合优化各种工艺参数而显着降低。 可以控制第一组工艺参数以对其中沉积阻挡层的处理室进行预处理。 可以控制第二组工艺参数，以在阻挡层沉积之前最小化去除CuO期间铜层暴露的能量。 可以控制第三组工艺参数以最小化除去氧化铜后的热预算。