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    Method of making a semiconductor structure for high power semiconductor devices
    2.
    发明申请
    Method of making a semiconductor structure for high power semiconductor devices 有权
    制造大功率半导体器件的半导体结构的方法

    公开(公告)号：US20060088978A1

    公开(公告)日：2006-04-27

    申请号：US11248195

    申请日：2005-10-13

    Applicant: Rowland Clarke ,  Robert Howell ,  Michael Aumer

    Inventor： Rowland Clarke ,  Robert Howell ,  Michael Aumer

    IPC: H01L21/30

    CPC classification number: H01L21/76256 ,  H01L21/76254 ,  H01L21/8213 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/735 ,  H01L29/7787

    Abstract: A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO2 and a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiO2 of the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.

    Abstract translation: 用于大功率半导体器件的衬底布置包括在SiC晶片的表面上沉积有Si层的SiC晶片。 具有第一Si层，SiO 2中间层和Si第三层的SOI结构具有与沉积在SiC晶片上的Si结合的第三层Si，形成单一结构 。 除去SOI的第一层Si和SiO 2的中间层，留下可以制造各种半导体器件的纯的第三层Si。 可以在衬底布置的一部分上去除第三层Si和沉积的Si层，使得可以在SiC晶片上制造一个或多个半导体器件，而其他半导体器件可以容纳在纯的第三层Si上。

    HEMT device and method of making
    3.
    发明申请
    HEMT device and method of making 有权

    公开(公告)号：US20060057790A1

    公开(公告)日：2006-03-16

    申请号：US10938602

    申请日：2004-09-13

    Applicant: Rowland Clarke ,  Michael Aumer

    Inventor： Rowland Clarke ,  Michael Aumer

    IPC: H01L21/338

    CPC classification number: H01L29/7788 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7789

    Abstract: A HEMT type device which has pillars with vertical walls perpendicular to a substrate. The pillars are of an insulating semiconductor material such as GaN. Disposed on the side surfaces of the pillars is a barrier layer of a semiconductor material such as AlGaN having a bandgap greater than that of the insulating material of the pillars. Electron flow is confined to a narrow channel at the interface of the two materials. Suitable source, drain and gate contacts are included for HEMT operation.

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