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    DIE STRUCTURE, MANUFACTURING METHOD AND SUBSTRATE THEREOF
    1.
    发明申请
    DIE STRUCTURE, MANUFACTURING METHOD AND SUBSTRATE THEREOF 有权
    DIE结构，制造方法及其基板

    公开(公告)号：US20120168950A1

    公开(公告)日：2012-07-05

    申请号：US13186411

    申请日：2011-07-19

    申请人： Meng-Chi Huang ,  Han-Ping Yang ,  Min-Chieh Chou ,  Tune-Hune Kao ,  Jung-Kang Peng ,  Cheng-Hsuan Lin ,  Jian-Shian Lin

    发明人： Meng-Chi Huang ,  Han-Ping Yang ,  Min-Chieh Chou ,  Tune-Hune Kao ,  Jung-Kang Peng ,  Cheng-Hsuan Lin ,  Jian-Shian Lin

    IPC分类号： H01L23/48 ,  H01L21/50

    CPC分类号： H01L33/0079 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2933/0075 ,  H01L2924/00014

    摘要： A die structure, a manufacturing method and a substrate, wherein the die structure is constituted by a chip on wafer (COW) and the substrate, and the substrate is formed by stacking and then cutting a plurality of thermal and electrical conductive poles and a plurality of insulating material layers. Moreover, the fabricating of the die structure comprises a plurality of COWs carried on a carrier board is bonded on the substrate, the plurality of COWs are in contact with the plurality of thermal and electrical conductive poles on the substrate, and then the carrier board is removed. After that, a phosphor plate is adhered on the plurality of COWs so as to form a stacked structure. Thereafter, the stacked structure is cut, thus forming a plurality of die structures having at least one COW.

    摘要翻译： 模具结构，制造方法和基板，其中，所述模具结构由晶片上的芯片（COW）和所述基板构成，所述基板通过层叠形成，然后切割多个导热极和多个导电极 的绝缘材料层。 此外，模具结构的制造包括承载在载体板上的多个COW结合在基板上，多个COW与基板上的多个热导电极接触，然后载板是 删除。 之后，在多个COW上粘接荧光体板，形成层叠结构。 此后，切割堆叠结构，从而形成具有至少一个COW的多个模具结构。

    CONDUCTIVE FILM STRUCTURE, FABRICATION METHOD THEREOF, AND CONDUCTIVE FILM TYPE PROBE DEVICE FOR ICS
    2.
    发明申请
    CONDUCTIVE FILM STRUCTURE, FABRICATION METHOD THEREOF, AND CONDUCTIVE FILM TYPE PROBE DEVICE FOR ICS 审中-公开
    导电膜结构及其制造方法及ICS导电膜型探针装置

    公开(公告)号：US20100164517A1

    公开(公告)日：2010-07-01

    申请号：US12426695

    申请日：2009-04-20

    申请人： Min-Chieh CHOU ,  Tune-Hune KAO ,  Jen-Hui TSAI

    发明人： Min-Chieh CHOU ,  Tune-Hune KAO ,  Jen-Hui TSAI

    IPC分类号： G01R31/02 ,  H01B5/00 ,  H01B13/00

    CPC分类号： G01R31/2886 ,  G01R1/06744 ,  G01R1/06761 ,  G01R1/073 ,  G01R3/00

    摘要： A method for forming a conductive film structure is provided, which includes: providing an insulating substrate having a surface; forming a plurality of trenches in the surface of the insulating substrate, wherein the trenches are extended substantially parallel to each other; disposing the insulating substrate into a plating solution and plating conducting layers within the trenches to form a plurality of micro-wires; and stacking a plurality of the insulating substrates or winding or folding the insulating substrate along an axis substantially parallel to an extended direction of the micro-wires to form a conducting lump.

    摘要翻译： 提供一种形成导电膜结构的方法，其包括：提供具有表面的绝缘基板; 在所述绝缘基板的表面中形成多个沟槽，其中所述沟槽基本上彼此平行地延伸; 将所述绝缘基板设置在电镀液中，并对所述沟槽内的导电层进行电镀以形成多根微线; 并且堆叠多个绝缘基板或者沿着基本上平行于微线的延伸方向的轴线缠绕或折叠绝缘基板以形成导电块。

    Integrated compound nano probe card and method of making same
    3.
    发明授权
    Integrated compound nano probe card and method of making same 有权
    综合复合纳米探针卡及其制作方法

    公开(公告)号：US07671612B2

    公开(公告)日：2010-03-02

    申请号：US12071312

    申请日：2008-02-20

    申请人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    发明人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    IPC分类号： G01R31/02

    CPC分类号： G01R1/06755 ,  B82Y10/00 ,  B82Y30/00 ,  G01R1/07314 ,  G01R3/00 ,  H01L2924/00013 ,  Y10S977/742 ,  H01L2224/29099

    摘要： An integrated compound nano probe card is disclosed to include a substrate layer having a front side and a back side, and compound probe pins arranged in the substrate layer. Each compound probe pin has a bundle of aligned parallel nanotubes/nanorods and a bonding material bonded to the bundle of aligned parallel nanotubes/nanorods and filled in gaps in the nanotubes/nanorods. Each compound probe pin has a base end exposed on the back side of the substrate layer and a distal end spaced above the front side of the substrate layer.

    摘要翻译： 公开了一种集成化合物纳米探针卡，其包括具有前侧和背侧的基底层和布置在基底层中的复合探针。 每个复合探针都具有一对排列的平行的纳米管和纳米棒，以及粘合到对齐的平行纳米管/纳米棒束上并且填充在纳米管/纳米棒中的间隙中的粘合材料。 每个复合探针具有暴露在基底层的背面上的基端和在基底层的前侧间隔开的远端。

    Integrated compound nano probe card
    7.
    发明授权
    Integrated compound nano probe card 有权
    综合复合纳米探针卡

    公开(公告)号：US07652492B2

    公开(公告)日：2010-01-26

    申请号：US12071311

    申请日：2008-02-20

    申请人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    发明人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    IPC分类号： G01R31/02

    CPC分类号： G01R1/06755 ,  B82Y10/00 ,  B82Y30/00 ,  G01R1/07314 ,  G01R3/00 ,  H01L2924/00013 ,  Y10S977/742 ,  H01L2224/29099

    摘要： An integrated compound nano probe card is disclosed to include a substrate layer having a front side and a back side, and compound probe pins arranged in the substrate layer. Each compound probe pin has a bundle of aligned parallel nanotubes/nanorods and a bonding material bonded to the bundle of aligned parallel nanotubes/nanorods and filled in gaps in the nanotubes/nanorods. Each compound probe pin has a base end exposed on the back side of the substrate layer and a distal end spaced above the front side of the substrate layer.

    摘要翻译： 公开了一种集成化合物纳米探针卡，其包括具有前侧和背侧的基底层和布置在基底层中的复合探针。 每个复合探针都具有一对排列的平行的纳米管和纳米棒，以及粘合到对齐的平行纳米管/纳米棒束上并且填充在纳米管/纳米棒中的间隙中的粘合材料。 每个复合探针具有暴露在基底层的背面上的基端和在基底层的前侧间隔开的远端。

    Integrated compound nano probe card and method of making same
    8.
    发明授权
    Integrated compound nano probe card and method of making same 有权
    综合复合纳米探针卡及其制作方法

    公开(公告)号：US07585548B2

    公开(公告)日：2009-09-08

    申请号：US12071310

    申请日：2008-02-20

    申请人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    发明人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    IPC分类号： B05D5/00

    CPC分类号： G01R1/06755 ,  B82Y10/00 ,  B82Y30/00 ,  G01R1/07314 ,  G01R3/00 ,  H01L2924/00013 ,  Y10S977/742 ,  H01L2224/29099

    摘要： An integrated compound nano probe card is disclosed to include a substrate layer having a front side and a back side, and compound probe pins arranged in the substrate layer. Each compound probe pin has a bundle of aligned parallel nanotubes/nanorods and a bonding material bonded to the bundle of aligned parallel nanotubes/nanorods and filled in gaps in the nanotubes/nanorods. Each compound probe pin has a base end exposed on the back side of the substrate layer and a distal end spaced above the front side of the substrate layer.

    摘要翻译： 公开了一种集成化合物纳米探针卡，其包括具有前侧和背侧的基底层和布置在基底层中的复合探针。 每个复合探针都具有一对排列的平行的纳米管和纳米棒，以及粘合到对齐的平行纳米管/纳米棒束上并且填充在纳米管/纳米棒中的间隙中的粘合材料。 每个复合探针具有暴露在基底层的背面上的基端和在基底层的前侧间隔开的远端。

    Integrated complex nano probe card and method of making same
    9.
    发明授权
    Integrated complex nano probe card and method of making same 有权
    集成复合纳米探针卡及其制作方法

    公开(公告)号：US07400159B2

    公开(公告)日：2008-07-15

    申请号：US10393262

    申请日：2003-03-21

    申请人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    发明人： Horng-Jee Wang ,  Ya-Ru Huang ,  Min-Chieh Chou

    IPC分类号： G01R31/02

    CPC分类号： G01R1/06755 ,  B82Y10/00 ,  B82Y30/00 ,  G01R1/07314 ,  G01R3/00 ,  H01L2924/00013 ,  Y10S977/742 ,  H01L2224/29099

    摘要： An integrated complex nano probe card is disclosed to include a substrate layer having a front side and a back side, and complex probe pins arranged in the substrate layer. Each complex probe pin has a bundle of aligned parallel nanotubes/nanorods and a bonding material bonded to the bundle of aligned parallel nanotubes/nanorods and filled in gaps in the nanotubes/nanorods. Each complex probe pin has a base end exposed on the back side of the substrate layer and a distal end spaced above the front side of the substrate layer.

    摘要翻译： 公开了一种集成的复合纳米探针卡，其包括具有前侧和后侧的基底层，以及布置在基底层中的复杂探针。 每个复合探针都具有一束对准的平行纳米管/纳米棒，以及粘合到对齐的平行纳米管/纳米棒的束并且填充在纳米管/纳米棒中的间隙中的粘合材料。 每个复合探针具有暴露在基底层的背面上的基端和在基底层的前侧间隔开的远端。

    MULTI-LAYER ELECTRIC PROBE AND FABRICATING METHOD THEREOF
    10.
    发明申请
    MULTI-LAYER ELECTRIC PROBE AND FABRICATING METHOD THEREOF 审中-公开
    多层电动探头及其制造方法

    公开(公告)号：US20080094084A1

    公开(公告)日：2008-04-24

    申请号：US11616892

    申请日：2006-12-28

    申请人： Meng-Chi Huang ,  Min-Chieh Chou ,  Fuh-Yu Chang ,  Ching-Ping Wu

    发明人： Meng-Chi Huang ,  Min-Chieh Chou ,  Fuh-Yu Chang ,  Ching-Ping Wu

    IPC分类号： G01R31/02 ,  H01R43/00

    CPC分类号： G01R1/06711 ,  G01R1/06761 ,  G01R3/00 ,  Y10T29/49002 ,  Y10T29/49117

    摘要： A multi-layer electric probe, suitable for testing a to-be-tested device, includes a first strip layer and a second strip layer. The first strip layer has a first conductivity and a first mechanical strength. The second strip layer has a second conductivity and a second mechanical strength. The first strip layer and the second strip layer are solidly adhered together as a structural body so as to produce at least one of the desired capabilities of enduring current and mechanical strength. The multi-layer electric probe can further include at least a third strip layer having the capability of enduring current and the desired mechanical strength.

    摘要翻译： 适用于测试待测试装置的多层电探针包括第一条带层和第二条带层。 第一带状层具有第一导电性和第一机械强度。 第二带状层具有第二导电性和第二机械强度。 第一带层和第二带层作为结构体牢固地粘合在一起，以便产生持久电流和机械强度的期望能力中的至少一个。 多层电探​​针还可以包括具有耐久电流和期望的机械强度的能力的至少第三带状层。