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    Method of forming and etching a resist protect oxide layer including end-point etch
    2.
    发明授权
    Method of forming and etching a resist protect oxide layer including end-point etch 有权
    形成和蚀刻包括终点蚀刻的抗蚀剂保护氧化物层的方法

    公开(公告)号：US06348389B1

    公开(公告)日：2002-02-19

    申请号：US09266312

    申请日：1999-03-11

    申请人： Chen Cheng Chou ,  Tzong-Sheng Chang

    发明人： Chen Cheng Chou ,  Tzong-Sheng Chang

    IPC分类号： H01L21336

    CPC分类号： H01L21/31116

    摘要： The present invention provides a method for forming and etching a resist protect oxide layer, of which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window. The process begins by forming a shallow trench isolation on a semiconductor substrate. The semiconductor substrate has a first area and a second area separated by the shallow trench isolation. A gate is formed on the semiconductor substrate in the first area, adjacent to the shallow trench isolation. In a key step, a resist protect oxide layer comprising a thin silicon oxide layer and an overlying thin nitrogen containing layer, is deposited over the semiconductor substrate, the gate, and the shallow trench isolation. The thin nitrogen containing layer can be composed of silicon nitride or silicon oxynitride. Alternatively, if the notrogen containing layer is composed of silicon oxynitride, the oxide layer can be omitted because oxynitride's stress is less than nitrogen, so the oxynitride could use a native oxide layer as the buffer oxide. The resist protect oxide layer is patterned in an RPO etch step; thereby exposing the first area, including the source and drain regions. A key advantage of the invention is that the RPO etch step can be performed in an endpoint mode where the endpoint is detected by the nitrogen content of the etch chamber ambient. Silicide regions can then be formed on the source and drain regions. A second key advantage of the invention is that the nitrogen containing layer of the resist protect oxide layer has a slower etch rate during pre-metal dip than a resist protect oxide layer composed of only oxide.

    摘要翻译： 本发明提供了形成和蚀刻抗蚀剂保护氧化物层的方法，其提供了对浅沟槽隔离的改进的蚀刻选择性和增加的预金属浸渍处理窗口。 该过程开始于在半导体衬底上形成浅沟槽隔离。 半导体衬底具有通过浅沟槽隔离分离的第一区域和第二区域。 在第一区域中的半导体衬底上形成栅极，与浅沟槽隔离相邻。 在关键步骤中，在半导体衬底，栅极和浅沟槽隔离之上沉积包括薄氧化硅层和上覆的含氮氮层的抗蚀剂保护氧化物层。 薄氮层可以由氮化硅或氮氧化硅构成。 或者，如果含有氢氧化镁的层由氮氧化硅构成，则由于氧氮化物的应力小于氮而能够省略氧化层，因此氮氧化物可以使用天然氧化物层作为缓冲氧化物。 抗蚀剂保护氧化物层在RPO蚀刻步骤中被图案化; 从而暴露包括源区和漏区的第一区。 本发明的一个关键优点是RPO蚀刻步骤可以以端点模式进行，其中端点由蚀刻室环境的氮含量检测。 然后可以在源区和漏区上形成硅化物区域。 本发明的第二个关键优点是抗蚀剂保护氧化物层的含氮层在预金属浸渍期间比仅由氧化物构成的抗蚀剂保护氧化物层具有较慢的蚀刻速率。

    Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure
    3.
    发明授权
    Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure 失效
    用于使用氮化硅间隔物和自对准接触结构的MOSFET器件与电容器结构集成的工艺

    公开(公告)号：US5766992A

    公开(公告)日：1998-06-16

    申请号：US827814

    申请日：1997-04-11

    申请人： Chen Cheng Chou ,  Jenn Tsao

    发明人： Chen Cheng Chou ,  Jenn Tsao

    IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/8242

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： A semiconductor fabrication process, allowing integration of MOSFET devices, and capacitor structures, on a single semiconductor chip, has been developed. The process integration features the use of a MOSFET device, fabricated using a self-aligned contact structure, allowing a reduction in the source and drain area needed for contact. Silicon nitride spacers, used on the sides of the polysilicon gate electrode, protect the polysilicon gate structure, during the opening of a self-aligned contact hole.

    摘要翻译： 已经开发了半导体制造工艺，允许在单个半导体芯片上集成MOSFET器件和电容器结构。 该工艺集成特征在于使用使用自对准接触结构制造的MOSFET器件，允许减少接触所需的源极和漏极面积。 用于多晶硅栅电极侧面的氮化硅间隔物在开放自对准接触孔期间保护多晶硅栅极结构。

    Non-distort spacer profile during subsequent processing
    6.
    发明授权
    Non-distort spacer profile during subsequent processing 有权
    后续处理期间的非变形间隔图

    公开(公告)号：US06346449B1

    公开(公告)日：2002-02-12

    申请号：US09312599

    申请日：1999-05-17

    申请人： Tzong-Sheng Chang ,  Shih-Chang Huang ,  Bor-Zen Tien ,  Chen Cheng Chou

    发明人： Tzong-Sheng Chang ,  Shih-Chang Huang ,  Bor-Zen Tien ,  Chen Cheng Chou

    IPC分类号： H01L21331

    CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/28061 ,  H01L21/31111 ,  H01L21/31116

    摘要： A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The process begins by providing a substrate structure having a gate thereon. Sidewall spacers are formed on the sidewalls of the gate. Impurity ions are implanted into the substrate structure adjacent to the gate to form source and drain regions. A resist protect oxide layer is formed over the substrate structure. The resist protect oxide is patterned by forming a mask over the resist protect oxide layer having an opening over the gate and the source and drain regions. The resist protect oxide layer is selectively etched; thereby removing the resist protect oxide over the source and drain regions without distorting the sidewall spacers. A silicide region is formed on the source and drain regions using a salicide process comprising a pre-amorphous implant and one or more rapid thermal anneal steps. The undistorted sidewall spacers reduce the distance that pre-amorphous implant damage extends under the gate during subsequent processing, which reduces the damage induced impurity ion diffusion under the gate. Because there is less impurity ion diffusion under the gate, junction depletion and source to drain leakage are reduced.

    摘要翻译： 一种用于制造用于场效应晶体管的结的方法，该场效应晶体管在随后的处理期间不会引起侧壁间隔物的变形，从而减少结耗尽和漏源泄漏。 该过程开始于提供其上具有栅极的衬底结构。 侧壁间隔件形成在门的侧壁上。 将杂质离子注入到与栅极相邻的衬底结构中以形成源区和漏区。 在衬底结构上形成抗蚀剂保护氧化物层。 通过在具有在栅极和源极和漏极区域上的开口的抗蚀剂保护氧化物层上形成掩模来对抗蚀剂保护氧化物进行图案化。 选择性地蚀刻抗蚀剂保护氧化物层; 从而在源极和漏极区域上除去抗蚀剂保护氧化物，而不会使侧壁间隔物变形。 使用包括预非晶态植入物和一个或多个快速热退火步骤的自对准硅化物工艺在源极和漏极区域上形成硅化物区域。 未失真的侧壁间隔物减小了在随后的处理期间预非晶体注入损伤在栅极下延伸的距离，这减少了栅极下的损伤引起的杂质离子扩散。 因为栅极下的杂质离子扩散较少，所以结耗尽和源极漏极漏极减少。

    Method for salicide process using a titanium nitride barrier layer
    7.
    发明授权
    Method for salicide process using a titanium nitride barrier layer 有权
    使用氮化钛阻挡层的自对准硅化物工艺的方法

    公开(公告)号：US06284611B1

    公开(公告)日：2001-09-04

    申请号：US09467134

    申请日：1999-12-20

    申请人： Bor-Zen Tien ,  Tzong-Sheng Chang ,  Chen-Cheng Chou ,  Wen-Jye Yue

    发明人： Bor-Zen Tien ,  Tzong-Sheng Chang ,  Chen-Cheng Chou ,  Wen-Jye Yue

    IPC分类号： H01L21336

    CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/4933

    摘要： This invention provides a method for forming a self-aligned silicide with low sheet resistance in the N+ source and drain regions and the N+ polysilicon regions in a semiconductor device using a titanium nitride barrier layer to prevent nitridation of an underlying titanium layer during rapid thermal anneal. The process begins by providing a substrate structure having a gate thereon. A titanium layer is deposited over the substrate structure and the gate. Mixing ions are implanted through the titanium layer into source and drain regions adjacent to the gate. A titanium nitride barrier layer is deposited on the titanium layer. The substrate structure is rapid thermal annealed causing the titanium layer to react with the underlying silicon to form silicide. The substrate structure is selectively etched to remove the titanium nitride barrier layer and unreacted titanium. A second rapid thermal anneal is performed.

    摘要翻译： 本发明提供了一种用于在半导体器件中使用氮化钛阻挡层在N +源极和漏极区域以及N +多晶硅区域中形成具有低薄层电阻的自对准硅化物的方法，以防止在快速热退火期间下层钛层的氮化 。 该过程开始于提供其上具有栅极的衬底结构。 在衬底结构和栅极上沉积钛层。 混合离子通过钛层注入与栅极相邻的源区和漏区。 氮化钛阻挡层沉积在钛层上。 衬底结构是快速热退火，导致钛层与下面的硅反应形成硅化物。 选择性地蚀刻衬底结构以除去氮化钛阻挡层和未反应的钛。 进行第二次快速热退火。

    Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)
    8.
    发明授权
    Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC) 失效
    制造改进的多晶硅栅极电极结构和侧壁间隔物的方法，用于更可靠的自对准触点（SAC）

    公开(公告)号：US5817562A

    公开(公告)日：1998-10-06

    申请号：US789212

    申请日：1997-01-24

    申请人： Tzong-Sheng Chang ,  Chen-Cheng Chou ,  Jenn Tsao

    发明人： Tzong-Sheng Chang ,  Chen-Cheng Chou ,  Jenn Tsao

    IPC分类号： H01L21/60 ,  H01L21/336

    CPC分类号： H01L21/76897

    摘要： A method was achieved for making FET stacked gate electrode structures with improved sidewall profiles. These more vertical sidewalls improve the control tolerance of the gate electrode length (L.sub.eff) and improve the shape of the sidewall spacers for making more reliable metal contacts to the self-aligned source/drain contact areas. The method uses a stacked gate electrode layer having a TEOS oxide and a hard mask of silicon nitride on the gate electrode polysilicon layer. During patterning of the stacked gate electrode structure using a photoresist mask, the hard mask minimizes the buildup of a polymer on the TEOS oxide sidewall. This polymer would otherwise act as a masking material resulting in an abrupt step at the TEOS oxide/polysilicon interface when the polysilicon etch is completed. This results in improved gate electrode line length tolerance and much improved sidewall spacers that minimize electrical shorts between the metal source/drain contacts and the polysilicon gate electrodes.

    摘要翻译： 实现了具有改进的侧壁轮廓的FET叠层栅电极结构的方法。 这些更垂直的侧壁提高了栅电极长度（Leff）的控制公差，并且改善了侧壁间隔件的形状，以使得更为可靠的金属接触到自对准的源极/漏极接触区域。 该方法在栅电极多晶硅层上使用具有TEOS氧化物和氮化硅的硬掩模的堆叠栅极电极层。 在使用光致抗蚀剂掩模的堆叠栅极电极结构的图案化期间，硬掩模使聚合物在TEOS氧化物侧壁上的积聚最小化。 否则，当多晶硅蚀刻完成时，该聚合物将用作掩模材料，导致在TEOS氧化物/多晶硅界面处的突然的步骤。 这导致改善的栅电极线长度公差和大大改进的侧壁间隔件，其使金属源极/漏极触点和多晶硅栅电极之间的电短路最小化。

    THREE-DIMENSIONAL GLASSES AND METHOD FOR OPERATING THE SAME
    9.
    发明申请
    THREE-DIMENSIONAL GLASSES AND METHOD FOR OPERATING THE SAME 审中-公开
    三维玻璃及其操作方法

    公开(公告)号：US20130002654A1

    公开(公告)日：2013-01-03

    申请号：US13436987

    申请日：2012-04-01

    申请人： Tse-Fan Yeh ,  Chen-Cheng Chou ,  Chun-Chieh Chen ,  Shu-Hui Liao ,  Jeng-An Liao ,  Chun-Hao Chen

    发明人： Tse-Fan Yeh ,  Chen-Cheng Chou ,  Chun-Chieh Chen ,  Shu-Hui Liao ,  Jeng-An Liao ,  Chun-Hao Chen

    IPC分类号： G06T15/00

    CPC分类号： G08C23/04 ,  G02B27/2264 ,  H04N13/341 ,  H04N13/398

    摘要： A three-dimensional (3D) glasses and a method for operating the same are provided. The 3D glasses includes a first lens, a second lens, an infrared receiver and a control unit. The infrared receiver receives an infrared signal to output a digital control signal. The control unit is coupled to the infrared receiver. The control unit controls a first state of the first lens and a second state of the second lens according to a first pulse of the digital control signal, where at least one of the first state and the second state is an OFF state.

    摘要翻译： 提供三维（3D）眼镜及其操作方法。 3D眼镜包括第一透镜，第二透镜，红外接收器和控制单元。 红外线接收器接收红外信号以输出数字控制信号。 控制单元耦合到红外接收器。 控制单元根据数字控制信号的第一脉冲控制第一透镜的第一状态和第二透镜的第二状态，其中第一状态和第二状态中的至少一个为OFF状态。