公开(公告)号：US5381046A

公开(公告)日：1995-01-10

申请号：US160470

申请日：1993-12-01

申请人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

发明人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L29/52 ,  H01L29/54

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/904

摘要： A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al.sub.2 O.sub.3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof. A second thick passivating layer is formed above the resulting structure having a set of second metal contact studs therein. The second metal studs contact at least one of the polysilicon lands and/or one of the first contact studs. The top surface of the second contact studs is coplanar with the top surface of the second thick passivating layer. A plurality of metal lands is formed above the second thick passivating layer and in contact with the second contact studs. A final insulating film insulates and passivates the metal lands.

摘要翻译： 一种半导体结构，用于在CMOS FET技术中制造具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM。 该结构由其中具有器件的有源区的半导体衬底形成，并且在其上形成多晶硅线。 第一厚钝化层由衬底上方的蚀刻停止层和磷硅酸盐玻璃（PSG）层形成。 通过第一厚钝化层的一组第一金属触头柱接触有源区和/或多晶硅线中的至少一个。 蚀刻停止层（26）可以是本征多晶硅或Al 2 O 3。 第一接触柱的顶表面与第一厚钝化层的顶表面共面。 形成在平面结构上的多个多晶硅焊盘与第一触头柱接触。 多晶硅焊盘是高电阻性，高导电性或其混合物。 在所得结构之上形成第二厚钝化层，其中具有一组第二金属接触柱。 第二金属螺柱接触至少一个多晶硅焊盘和/或第一接触螺柱之一。 第二接触柱的顶表面与第二厚钝化层的顶表面共面。 多个金属焊盘形成在第二厚钝化层之上并且与第二接触柱接触。 最终的绝缘膜绝缘并钝化金属焊盘。

公开(公告)号：US5155572A

公开(公告)日：1992-10-13

申请号：US680490

申请日：1991-04-04

申请人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

发明人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74

CPC分类号： H01L29/74 ,  H01L29/0821

摘要： A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).

摘要翻译： 垂直隔离集电极PNP晶体管结构（58）包括分别形成发射极，基极和集电极的P +区（45），N区（44）和P-阱区（46）。 P阱区被包围在与N +掩埋层（48）和N接触区域（47）组成的N型槽中。 到P阱区域（46）和N到达区域（47）的接触区域（46-1,47-1）被短路以限定公共集电极接触件（59）。 此外，P阱区域（46）的厚度W被最小化以允许由N PNP基区（44），P-阱区（46）和N +掩埋层形成的寄生NPN晶体管的晶体管作用， （48）分别作为所述PNP晶体管的集电极，基极和发射极。 PNP晶体管结构（67）可以与传统的NPN晶体管结构（61）组合。

公开(公告)号：US5100817A

公开(公告)日：1992-03-31

申请号：US729250

申请日：1991-07-12

申请人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

发明人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/11 ,  H01L21/8221 ,  H01L27/1108

摘要： A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . . ) formed on the said thick passivating layer, certain portions of said first polysilicon lands defining the source, drain and channel regions forming the body of a PFET device with at least one region (SP1) contacting one of said first metal contact studs; a thin insulating layer (33) forming the gate dielectric layer of said PFET device; a plurality of highly doped second polysilicon lands (35-1A, . . . ) formed over by said thin insulating layer (33); a certain portion of said second polysilicon lands (35-1A, . . . ) forming the gate electrode (GP1) of said PFET device (SP1) which is self-aligned with said source (SP1) and drain (DP1) regions; a second thick passivating layer (37/38) having a set of second metal contact studs (40-1, . . . ) therein contacting at least one of said first or second polysilicon lands (31-1, . . . ; 35-1, . . . ) and/or said first contact studs (30-1, . . . ); the surface of said second metal contact studs is coplanar with the surface of said second thick passivating layer; a first metal interconnection configuration having metal lands (41-1, . . . ) electrically contacting at least one of said second metal contact studs (40-1, . . . ); and, a final insulating film (42).

公开(公告)号：US6022754A

公开(公告)日：2000-02-08

申请号：US120755

申请日：1998-07-22

申请人： Jean-Paul Guillemet ,  Myriam Combes ,  Stephane Astie ,  Emmanuel Scheid

发明人： Jean-Paul Guillemet ,  Myriam Combes ,  Stephane Astie ,  Emmanuel Scheid

IPC分类号： G01L9/00 ,  G01K7/00 ,  G01N27/12 ,  H01L29/84

CPC分类号： G01N27/12 ,  H01L2224/19

摘要： An electronic device comprises a semiconductor substrate (2) having a cavity (32) extending into the substrate (2), a membrane (8) formed over the semiconductor substrate so as to extend across the cavity (32) in the semiconductor substrate and an active region (14, 30) supported by the membrane (8) and positioned adjacent the cavity (32). The membrane (8) comprises a single dielectric layer formed of an oxy-nitride material.

摘要翻译： 电子设备包括具有延伸到基板（2）中的空腔（32）的半导体基板（2），形成在半导体基板上方以跨过半导体基板中的空腔（32）延伸的膜（8） 活性区域（14,30），由膜（8）支撑并且邻近空腔（32）定位。 膜（8）包括由氧化氮材料形成的单个电介质层。

公开(公告)号：US5691226A

公开(公告)日：1997-11-25

申请号：US672522

申请日：1996-06-25

申请人： Juergen Foerstner ,  Myriam Combes ,  Arlette Marty-Blavier ,  Guy Hautekiet

发明人： Juergen Foerstner ,  Myriam Combes ,  Arlette Marty-Blavier ,  Guy Hautekiet

IPC分类号： H01L21/74 ,  H01L21/8249

CPC分类号： H01L21/74 ,  H01L21/8249 ,  Y10S148/009

摘要： A method of manufacturing both bipolar and CMOS devices including vertical PNP, NPN, PMOS and NMOS devices on the same chip, includes the steps of, simultaneously forming an N+ region (14) on part of a P base region (11) of the vertical NPN device to form the emitter contact region thereof, an N+ region (14) on a part of an N- epitaxial layer (5) of the vertical NPN device to form the collector contact region thereof, N+ regions (14) on first and second parts of a P well region (8) of the NMOS device to form the source and drain thereof, and an N+ region (14) on an N base region (9) of the vertical PNP device to form the base contact thereof. In a further simultaneous step, there are formed P+ regions (15) on the P-well (8) and N base (9) regions of the vertical PNP device to form the collector and emitter contact regions thereof, P+ regions (15) on first and second parts of the N- epitaxial layer (5) of the PMOS device to form the source and drain thereof, and a P+ region (15) on part of the P base region (11) of the vertical NPN device to form the base contact region thereof.

摘要翻译： 在同一芯片上制造包括垂直PNP，NPN，PMOS和NMOS器件的双极和CMOS器件的方法包括以下步骤：在垂直的P基极区域（11）的一部分上同时形成N +区域（14） NPN器件，以形成其发射极接触区域，在垂直NPN器件的N外延层（5）的一部分上的N +区域（14），以形成其集电极接触区域，第一和第二区域（14） 构成NMOS器件的P阱区域（8）的部分以形成其源极和漏极，以及在垂直PNP器件的N基极区域（9）上形成N +区域（14）以形成其基极接触。 在另一个同步步骤中，在P阱（8）和垂直PNP器件的N基极（9）区域上形成P +区（15），以形成其集电极和发射极接触区，P +区（15）在 PMOS器件的N外延层（5）的第一部分和第二部分以形成其源极和漏极，以及在垂直NPN器件的P基极区域（11）的一部分上的P +区域（15），以形成 其接触区域。

公开(公告)号：US5275963A

公开(公告)日：1994-01-04

申请号：US728929

申请日：1991-07-12

申请人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

发明人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L21/98

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/904

摘要： A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formedthereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39).The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology.The present invention also relates to the method for fabricating the same.

摘要翻译： 一种半导体结构，包括：其中形成有器件（T1 ...）的有源区（21）和/或在其上形成的多晶硅线（23-1 ...）的半导体衬底（18/19） 形成在衬底上方的第一厚钝化层（26/27），其具有一组第一金属触头柱（30-1 ...），其接触至少一个有源区（21）和/或多晶硅线（ 23-1，...）; 所述第一触头柱的表面与所述第一钝化层的表面共面; 形成在与所述第一触头柱接触的所述平面结构上的多个多晶硅焊盘（31-1 ...） 多晶硅焊盘是高电阻性，高导电性或其混合物; 形成在所得结构上方的第二厚钝化层（34/35），其具有一组第二金属触头螺柱（37-1 ...），其接触多晶硅焊盘中的至少一个和/或第一触头螺柱中的一个 ; 第二接触柱的表面与第二厚钝化层的表面共面。 形成在与第二接触柱接触的第二厚钝化层（34/35）上方的多个金属焊盘（38-1 ...） 最后的绝缘膜（39）。 本发明的结构可有利地用于在CMOS FET技术中实现具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM单元的芯片中。 本发明还涉及其制造方法。

公开(公告)号：US5112765A

公开(公告)日：1992-05-12

申请号：US730736

申请日：1991-07-16

申请人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone ,  Vincent Vallet

发明人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone ,  Vincent Vallet

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/00 ,  H01L27/092 ,  H01L27/11

CPC分类号： H01L27/1108 ,  H01L21/76895 ,  H01L21/8221 ,  H01L27/11 ,  Y10S148/164

摘要： A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.

摘要翻译： 提供一种用于制造堆叠半导体结构的制造方法，包括：将第一厚钝化层沉积到基底结构上; 在所述第一厚钝化层中形成暴露至少一个有源区和/或所述多晶硅线之一的第一螺柱开口; 沉积导电材料的第一层以填充第一螺柱开口并限定第一接触螺柱，一些第一接触柱的上部包括PFET器件的栅电极; 平面化结构以使第一接触柱的顶表面与第一厚钝化层的表面共面; 沉积厚的绝缘层以形成PFET器件的栅极电介质，并将其图形化以限定接触开口，以在期望的位置暴露所选择的第一触头柱; 沉积一层多晶硅; 图案化多晶硅层以限定在期望位置处包含第一接触柱的多晶硅焊盘; 选择性地注入以限定PFET器件和互连导体的源区和漏区; 沉积盖层; 在所述第二厚钝化层中沉积形成第二螺柱孔的第二厚钝化层以暴露所述多晶硅焊盘的所述部分和/或所述第一触头柱的部分; 沉积第二层导电材料以限定第二接触柱; 并且平坦化该结构以使第二接触柱的顶表面与第二厚钝化层的表面共面。

公开(公告)号：US5691224A

公开(公告)日：1997-11-25

申请号：US668655

申请日：1996-06-25

申请人： Juergen Foerstner ,  Myriam Combes ,  Arlette Marty-Blavier ,  Guy Hautekiet

发明人： Juergen Foerstner ,  Myriam Combes ,  Arlette Marty-Blavier ,  Guy Hautekiet

IPC分类号： H01L27/06 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/70

CPC分类号： H01L21/8249 ,  H01L21/74 ,  Y10S148/009

摘要： A method of manufacturing an integrated circuit having a buried layer of a low doped type of conductivity (2) and a buried layer of a highly doped type of the same conductivity (3) by masking a substrate (1) so as to define open areas on the substrate where it is desired to provide the two buried layers and doping the open areas of the substrate with a low concentration of dopants to form the low doped type of buried layer (2) is formed. Then one open area where the low doped type of buried layer (2) is formed is masked and the other open area is doped with a high concentration of dopants to form the highly doped type of buried layer (3).

摘要翻译： 一种制造集成电路的方法，该集成电路具有通过掩蔽衬底（1）而具有低掺杂类型的导电性（2）的掩埋层和具有相同导电性（3）的高掺杂型掩埋层，以限定开放区域 在需要提供两个掩埋层的衬底上，并且形成具有低浓度掺杂剂以形成低掺杂型掩埋层（2）的衬底的开放区域。 然后，在其中形成低掺杂型掩埋层（2）的一个开放区域被掩蔽，并且另一个开放区域掺杂有高浓度的掺杂剂以形成高掺杂型掩埋层（3）。

公开(公告)号：US5320975A

公开(公告)日：1994-06-14

申请号：US34325

申请日：1993-03-22

申请人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

发明人： Carl Cederbaum ,  Roland Chanclou ,  Myriam Combes ,  Patrick Mone

IPC分类号： H01L21/8249 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/105 ,  H01L27/11 ,  H01L29/78 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1207 ,  H01L29/7838 ,  H01L27/105 ,  Y10S257/903

摘要： A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure, comprising the steps of: providing a P-type silicon substrate having a surface that includes a plurality of isolation regions; delineating polysilicon lands at selected isolation regions; forming N-well regions into the substrate at a location where bulk PFETs are to be subsequently formed; forming insulator encapsulated conductive polysilicon studs to provide gate electrodes at desired locations of the structure; forming self-aligned source/drain regions of the bulk NFETs into the substrate; forming self-aligned source/drain regions of the bulk PFETs and pPFETs into the substrate and into the polysilicon lands, respectively; and forming contact regions to the selected locations that include the source/drain regions. In particular, the method finds application in the formation of polysilicon PFETs which are extensively used as load devices in six device (6D) SRAM cells.

摘要翻译： 一种在CMOS或BiCMOS半导体结构中与本体PFET和NFET器件同时形成薄膜伪平面多晶硅栅极PFET（pPFET）的方法，包括以下步骤：提供具有表面的P型硅衬底，所述表面包括多个 隔离区; 在选定的隔离区划定多晶硅土地; 在随后形成体PFET的位置处形成N阱区域到衬底中; 形成绝缘体封装的导电多晶硅柱钉，以在结构的期望位置处提供栅电极; 将本体NFET的自对准源极/漏极区域形成到衬底中; 将本体PFET和pPFET的自对准源极/漏极区分别形成到衬底中并进入多晶硅焊盘; 以及将接触区域形成到包括源极/漏极区域的选定位置。 特别地，该方法可用于形成多晶硅PFET，其广泛用作六个器件（6D）SRAM单元中的负载器件。