公开(公告)号：US5155572A

公开(公告)日：1992-10-13

申请号：US680490

申请日：1991-04-04

申请人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

发明人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74

CPC分类号： H01L29/74 ,  H01L29/0821

摘要： A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).

摘要翻译： 垂直隔离集电极PNP晶体管结构（58）包括分别形成发射极，基极和集电极的P +区（45），N区（44）和P-阱区（46）。 P阱区被包围在与N +掩埋层（48）和N接触区域（47）组成的N型槽中。 到P阱区域（46）和N到达区域（47）的接触区域（46-1,47-1）被短路以限定公共集电极接触件（59）。 此外，P阱区域（46）的厚度W被最小化以允许由N PNP基区（44），P-阱区（46）和N +掩埋层形成的寄生NPN晶体管的晶体管作用， （48）分别作为所述PNP晶体管的集电极，基极和发射极。 PNP晶体管结构（67）可以与传统的NPN晶体管结构（61）组合。

公开(公告)号：US5023478A

公开(公告)日：1991-06-11

申请号：US493079

申请日：1990-03-13

申请人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

发明人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

IPC分类号： H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

CPC分类号： H03K19/013 ,  H03F1/308 ,  H03F3/3008 ,  H03F3/3071 ,  H03K17/667

摘要： The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration. As a result, the voltage shift VS between the base nodes is selected to have the said output transistors operating at an operating point which ensures minimum delay and power consumption. In a typical bipolar technology, VS is made to be approximately equal to 1.5V. Additional features comprise the connection of a capacitor (C) between the base nodes and resistances (R1, R2) to the base nodes. The preceding driving circuit may be a CMOS logic gate or an ECL logic circuit.

公开(公告)号：US4922135A

公开(公告)日：1990-05-01

申请号：US271124

申请日：1988-11-14

申请人： Pierre Mollier ,  Pascal Tannhof

发明人： Pierre Mollier ,  Pascal Tannhof

IPC分类号： H01L27/095 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0952

CPC分类号： H03K19/09436 ,  H03K19/01721

摘要： The present invention relates to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A 3 way OR/NOR circuit of this invention includes a standard differential amplifier, the first branch of which is controlled by logic input signals. The second branch includes a current switch controlled by a reference voltage. The differential amplifier provides first and second output signals simultaneously and complementary each other. The circuit further includes two push pull output buffers. The first output buffer comprises an active pull up device connected in series with an active pull down device, and the first circuit output signal is available at their common node or at the output terminal. The active pull up device is controlled by a first output signal of the differential amplifier, and the active pull down device is preferably controlled by the second output signal through an intermediate source follower buffer. The second output buffer is of similar structure. The depicted circuit is of the dual phase type. However, if only one phase of the circuit output signal is needed, the output buffer and the intermediate buffer can be eliminated. The number of devices can be even further reduced by eliminating the other remaining intermediate buffer.

公开(公告)号：US5089725A

公开(公告)日：1992-02-18

申请号：US604842

申请日：1990-10-26

申请人： Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

发明人： Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/013

摘要： The base circuit comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages and a push-pull output buffer stage connected between second and third supply voltages. The push-pull output buffer stage comprises a pull-up transistor and a pull-down transistor connected in series with the circuit output node coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by the preamplifier. Both branches of the preamplifier are tied at a first output node (M). The first branch comprises a logic block performing the desired logic function of the base circuit that is connected through a load rsistor to the second supply voltage. The logic block consists of three parallel-connected input NPN transistors, whose emitters are coupled together at the first output node for NOR operation. The second branch is comprised of a biasing/coupling block connected to the second supply voltage and coupled to the first output node and to the base (B) node of the pull-down transistor. This block ensures both the appropriate polarization of the nodes in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal from node M to node B in AC, when input transistors of the logic block are ON. and base nodes. An anti-saturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

摘要翻译： 基本电路包括连接在第一和第二电源电压之间的差分类型的自参考前置放大器（31）和连接在第二和第三电源电压之间的推挽输出缓冲级。 推挽输出缓冲级包括与耦合在其间的电路输出节点串联连接的上拉晶体管和下拉晶体管。 这些晶体管由前置放大器提供的互补和基本同时的信号S和＆amp; upbar＆S驱动。 前置放大器的两个分支都连接在第一个输出节点（M）上。 第一分支包括执行通过负载晶体管连接到第二电源电压的基本电路的期望逻辑功能的逻辑块。 逻辑块由三个并联的输入NPN晶体管组成，其发射极在第一个输出节点耦合在一起用于NOR运算。 第二分支包括连接到第二电源电压并耦合到第一输出节点和下拉晶体管的基极（B）节点的偏置/耦合模块。 该块在逻辑块的输入晶体管中确保DC中节点的适当极化，而不需要外部参考电压发生器和低阻抗路径，用于在AC中将节点M到节点B的输出信号快速信号传输 上。 和基本节点。 通常由肖特基势垒二极管（SBD）组成的抗饱和块（AB）可用于防止下拉晶体管（TDN）的饱和，从而进一步加速电路。

公开(公告)号：US5010257A

公开(公告)日：1991-04-23

申请号：US493014

申请日：1990-03-13

申请人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

发明人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

IPC分类号： H03K17/567 ,  H03K5/007 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/0136 ,  H03K19/09448 ,  H03K5/007

摘要： According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15). It is a characteristic of this embodiment that the structure of CMOS interface (C2) is always independent of the logic function implemented in the conventional BICMOS logic circuit (11). More generally, the CMOS interface circuit may have various physical implementations, however, it is always comprised of CMOS FETs and it becomes active at least in one of the GND to VBE or (VH-BE) to VH range.

公开(公告)号：US07254565B2

公开(公告)日：2007-08-07

申请号：US10137969

申请日：2002-05-03

申请人： Ghislain Imbert De Tremiolles ,  Pascal Tannhof

发明人： Ghislain Imbert De Tremiolles ,  Pascal Tannhof

IPC分类号： G06E1/00 ,  G06E3/00 ,  G06F15/18 ,  G06G7/00 ,  G06N3/00 ,  G06N3/08 ,  G06N3/04

CPC分类号： G06K9/6276 ,  G06N3/063

摘要： An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

摘要翻译： 公开了一种改进的人造神经网络（ANN），其包括常规ANN，数据库块以及比较和更新电路。 常规ANN由多个神经元形成，每个神经元具有专用于存储原型的原型存储器和距离评估器，以评估呈现给ANN的输入模式与存储在其中的原型之间的距离。 数据库块具有：所有原型以切片排列，每个切片能够存储最多数量的原型; 要呈现给ANN的输入模式或查询; 以及在识别/分类阶段期间进行评估的距离。 比较和更新电路将距离与先前发现的相同输入模式更新的距离进行比较，或将之前存储的距离进行比较。

公开(公告)号：US20070150621A1

公开(公告)日：2007-06-28

申请号：US11682547

申请日：2007-03-06

申请人： Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

发明人： Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

IPC分类号： G06F3/00

CPC分类号： G06K9/6202 ,  G06K9/00986

摘要： A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

公开(公告)号：US20050154916A1

公开(公告)日：2005-07-14

申请号：US10756904

申请日：2004-01-14

申请人： Marc Boulanger ,  Clark Jeffries ,  C. Kinard ,  Kerry Kravec ,  Ravinder Sabhikhi ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

发明人： Marc Boulanger ,  Clark Jeffries ,  C. Kinard ,  Kerry Kravec ,  Ravinder Sabhikhi ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

IPC分类号： H04L9/00 ,  H04L12/24 ,  H04L29/06

CPC分类号： H04L63/1416 ,  H04L63/1441

摘要： An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in an input data stream. Each PPDE comprises many processing units (PUs) each designed to store intrusion signatures as a sequence of data with selected operation codes. The PUs have configuration registers for selecting modes of pattern recognition. Each PU compares a byte at each clock cycle. If a sequence of bytes from the input pattern match a stored pattern, the identification of the PU detecting the pattern is outputted with any applicable comparison data. By storing intrusion signatures in many parallel PUs, the IDS can process network data at the NP processing speed. PUs may be cascaded to increase intrusion coverage or to detect long intrusion signatures.

摘要翻译： 入侵检测系统（IDS）包括耦合到用于存储程序和数据的存储器单元的网络处理器（NP）。 NP还耦合到一个或多个并行模式检测引擎（PPDE），其提供对输入数据流中的模式的高速并行检测。 每个PPDE包括许多处理单元（PU），每个处理单元被设计为将入侵签名存储为具有所选操作码的数据序列。 PU具有用于选择模式识别模式的配置寄存器。 每个PU在每个时钟周期比较一个字节。 如果来自输入模式的字节序列与存储的模式匹配，则用任何适用的比较数据输出检测模式的PU的识别。 通过在多个并行PU中存储入侵签名，IDS可以以NP处理速度处理网络数据。 PU可以级联以增加入侵覆盖或检测长入侵签名。

公开(公告)号：US06347309B1

公开(公告)日：2002-02-12

申请号：US09223478

申请日：1998-12-30

申请人： Ghislain Imbert De Tremiolles ,  Pascal Tannhof

发明人： Ghislain Imbert De Tremiolles ,  Pascal Tannhof

IPC分类号： G06N306

CPC分类号： G06K9/6271 ,  G06N3/063

摘要： The improved neural network of the present invention results from the combination of a dedicated logic block with a conventional neural network based upon a mapping of the input space usually employed to classify an input data by computing the distance between said input data and prototypes memorized therein. The improved neural network is able to classify an input data, for instance, represented by a vector A even when some of its components are noisy or unknown during either the learning or the recognition phase. To that end, influence fields of various and different shapes are created for each neuron of the conventional neural network. The logic block transforms at least some of the n components (A1, . . . , An) of the input vector A into the m components (V1, . . . , Vm) of a network input vector V according to a linear or non-linear transform function F. In turn, vector V is applied as the input data to said conventional neural network. The transform function F is such that certain components of vector V are not modified, e.g. Vk=Aj, while other components are transformed as mentioned above, e.g. Vi=Fi(A1, . . . , An). In addition, one (or more) component of vector V can be used to compensate an offset that is present in the distance evaluation of vector V. Because, the logic block is placed in front of the said conventional neural network any modification thereof is avoided.

摘要翻译： 本发明的改进的神经网络是基于通常用于通过计算所述输入数据与其中存储的原型之间的距离来对输入数据进行分类的输入空间的映射，将专用逻辑块与传统神经网络的组合。 改进的神经网络能够对例如由向量A表示的输入数据进行分类，即使在学习或识别阶段期间，其一些组件是噪声或未知的。 为此，为传统神经网络的每个神经元创建各种不同形状的影响场。 逻辑块根据线性或非线性将输入矢量A的n个分量（A1，...，An）中的至少一些变换成网络输入矢量V的m个分量（V1，...，Vm） 然后将矢量V作为输入数据施加到所述常规神经网络。 变换函数F使得向量V的某些分量不被修改，例如， Vk = Aj，而其它组分如上所述被转化，例如。 Vi = Fi（A1，...，An）。 另外，矢量V的一个（或多个）分量可以用于补偿矢量V的距离评估中存在的偏移。因为逻辑块被放置在所述传统神经网络的前面，所以避免了其任何修改 。

公开(公告)号：US20110227194A1

公开(公告)日：2011-09-22

申请号：US13052262

申请日：2011-03-21

申请人： Simon Jeannot ,  Pascal Tannhof

发明人： Simon Jeannot ,  Pascal Tannhof

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

摘要翻译： 一种用于在包括一系列金属水平和通孔级别的互连堆叠的金属层中形成电容结构的方法，包括以下步骤：在金属层面形成至少一个其中限定沟槽的导电轨道; 在结构上保形地形成绝缘层; 在沟槽中形成导电材料; 并平坦化结构。