公开(公告)号：US5898606A

公开(公告)日：1999-04-27

申请号：US841372

申请日：1997-04-30

申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7883

摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

摘要翻译： 在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。 因此，多个存储单元的阈值电压增加。 在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。 因此，所选存储单元的阈值电压降低。

公开(公告)号：US5745417A

公开(公告)日：1998-04-28

申请号：US661930

申请日：1996-06-11

申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7883

摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

公开(公告)号：US5659505A

公开(公告)日：1997-08-19

申请号：US509250

申请日：1995-07-31

申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda

发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C11/40

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7883

摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

摘要翻译： 在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。 因此，多个存储单元的阈值电压增加。 在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。 因此，所选存储单元的阈值电压降低。

公开(公告)号：US5338957A

公开(公告)日：1994-08-16

申请号：US110151

申请日：1993-08-23

申请人： Atsushi Fukumoto ,  Makoto Ohi ,  Hiroshi Onoda ,  Natsuo Ajika ,  Yuichi Kunori

发明人： Atsushi Fukumoto ,  Makoto Ohi ,  Hiroshi Onoda ,  Natsuo Ajika ,  Yuichi Kunori

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  G11C11/34

CPC分类号： H01L27/115

摘要： The width of a charge storage electrode and a control electrode in the column direction is set to be wider above an element isolation region than that above a channel region. Therefore, the capacitance between the control electrode and the charge storage electrode can be increased to improve the coupling ratio in a nonvolatile semiconductor memory device. Also, a first interconnection layer is equal in height above the control electrode and above the channel region, so that patterning of the first interconnection layer can be carried out easily and precisely.

摘要翻译： 在列方向上的电荷存储电极和控制电极的宽度被设定为比元件隔离区域高于沟道区域以上的宽度。 因此，可以增加控制电极和电荷存储电极之间的电容，以提高非易失性半导体存储器件中的耦合比。 此外，第一互连层在控制电极上方高于沟道区域的高度相等，使得可以容易且精确地执行第一互连层的图案化。

公开(公告)号：US5400278A

公开(公告)日：1995-03-21

申请号：US114229

申请日：1993-09-01

申请人： Yuichi Kunori ,  Natsuo Ajika ,  Hiroshi Onoda ,  Makoto Ohi ,  Atsushi Fukumoto

发明人： Yuichi Kunori ,  Natsuo Ajika ,  Hiroshi Onoda ,  Makoto Ohi ,  Atsushi Fukumoto

IPC分类号： H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.

摘要翻译： 在根据本发明的半导体存储器件中，在半导体衬底的主表面上的边界区域中的场氧化物膜上形成导电层。 在半导体衬底上形成有一个栅极绝缘膜和一个控制栅电极的存储单元阵列区域中，栅极绝缘膜插在其间。 栅极电极形成在外围电路区域中，栅极绝缘膜插入其间。 在导电层，栅电极和控制栅电极上形成层间绝缘膜。 在层间绝缘膜的预定位置处形成接触孔。 在包括接触孔的内表面的层间绝缘膜上选择性地形成布线层。 根据本发明，可以防止在边界区域的场氧化膜的表面上形成凹部。 也可以通过在边界区域的场氧化膜上形成导电层，并通过固定导电层的电位来保护存储单元阵列区域免受外部噪声的影响。

公开(公告)号：US5538912A

公开(公告)日：1996-07-23

申请号：US370755

申请日：1995-01-10

申请人： Yuichi Kunori ,  Natsuo Ajika ,  Hiroshi Onoda ,  Makoto Ohi ,  Atsushi Fukumoto

发明人： Yuichi Kunori ,  Natsuo Ajika ,  Hiroshi Onoda ,  Makoto Ohi ,  Atsushi Fukumoto

IPC分类号： H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.

摘要翻译： 在根据本发明的半导体存储器件中，在半导体衬底的主表面上的边界区域中的场氧化物膜上形成导电层。 在半导体衬底上形成有一个栅极绝缘膜和一个控制栅电极的存储单元阵列区域中，栅极绝缘膜插在其间。 栅极电极形成在外围电路区域中，栅极绝缘膜插入其间。 在导电层，栅电极和控制栅电极上形成层间绝缘膜。 在层间绝缘膜的预定位置处形成接触孔。 在包括接触孔的内表面的层间绝缘膜上选择性地形成布线层。 根据本发明，可以防止在边界区域的场氧化膜的表面上形成凹部。 也可以通过在边界区域的场氧化膜上形成导电层，并通过固定导电层的电位来保护存储单元阵列区域免受外部噪声的影响。

公开(公告)号：US5672533A

公开(公告)日：1997-09-30

申请号：US555414

申请日：1995-11-09

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5523596A

公开(公告)日：1996-06-04

申请号：US403614

申请日：1995-03-14

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L27/04 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  Y10S438/954

摘要： A capacitor includes a polycrystalline silicon layer 1 as a lower electrode layer, a dielectric layer 112, and a polycrystalline silicon layer 113 as an upper electrode layer. The dielectric layer 112 is formed by an oxynitride film 2, a silicon nitride film 3 and a top oxide film 4. A film thickness t.sub.3 of the top oxide film 4 is controlled to be less than 20 .ANG.. Capacitance of the capacitor can be increased while improving the duration of life of the dielectric layer, resulting in a highly reliable capacitor.

摘要翻译： 电容器包括作为下电极层的多晶硅层1，电介质层112和作为上电极层的多晶硅层113。 电介质层112由氧氮化物膜2，氮化硅膜3和顶部氧化物膜4形成。顶部氧化膜4的膜厚度t3被控制为小于20安培。 可以增加电容器的电容，同时改善电介质层的寿命，导致高度可靠的电容器。

公开(公告)号：US5233212A

公开(公告)日：1993-08-03

申请号：US692395

申请日：1991-04-25

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/76801 ,  H01L21/76834 ,  H01L27/10808 ,  Y10S257/90

摘要： A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.

摘要翻译： 半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了栅电极的顶部和侧壁。 在元件隔离区域（2）的表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁的绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于树脂膜的过度蚀刻而导致的断开。

公开(公告)号：US5338699A

公开(公告)日：1994-08-16

申请号：US10691

申请日：1993-01-29

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/76801 ,  H01L21/76834 ,  H01L27/10808 ,  Y10S257/90

摘要： A method of making a semiconductor device including a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) are smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resist film in patterning the conductive interconnection layer.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了顶部和侧壁 栅电极。 元件隔离区域（2）表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于抗蚀剂膜的过度蚀刻而导致的断开。