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    Semiconductor device having multiple semiconductor chips laminated together and electrically connected
    1.
    发明授权
    Semiconductor device having multiple semiconductor chips laminated together and electrically connected 有权

    公开(公告)号：US10553560B2

    公开(公告)日：2020-02-04

    申请号：US14776863

    申请日：2014-03-18

    申请人： PS4 Luxco S.a.r.l.

    发明人： Mitsuhisa Watanabe

    IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00

    摘要： A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other.

    Memory system and data transmission method
    2.
    发明授权
    Memory system and data transmission method 有权

    公开(公告)号：US10360953B2

    公开(公告)日：2019-07-23

    申请号：US15937518

    申请日：2018-03-27

    申请人： PS4 Luxco S.a.r.l

    发明人： Yoshinori Matsui

    IPC分类号： G11C7/10 ,  G11C29/50 ,  G11C29/02 ,  G11C11/4093 ,  G11C8/18 ,  G11C11/401 ,  G06F13/42

    摘要： A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

    Semiconductor device and manufacturing method thereof
    3.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10128250B2

    公开(公告)日：2018-11-13

    申请号：US14781149

    申请日：2014-03-26

    申请人： PS4 Luxco S.a.r.l.

    发明人： Yoshinori Ikebuchi

    IPC分类号： H01L27/108 ,  H01L21/76 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06 ,  H01L27/02

    摘要： One method for manufacturing a semiconductor device includes: forming provisional active regions that are shaped such that active regions that are adjacent in an X direction are connected to each other, forming a sacrificial film, performing etching, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions, embedding element-isolating insulating films in the first trenches and then removing the sacrificial film, forming first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films, embedding cap insulating films in second trenches that appear due to the formation of the second side-wall insulating films, and forming a plurality of third trenches at the positions of the second side-wall insulating films and forming word lines thereunder.

    Semiconductor device having internal voltage generating circuit
    4.
    发明授权
    Semiconductor device having internal voltage generating circuit 有权

    公开(公告)号：US10126765B2

    公开(公告)日：2018-11-13

    申请号：US15230902

    申请日：2016-08-08

    申请人： PS4 Luxco S.a.r.l.

    发明人： Koichiro Hayashi

    IPC分类号： G05F1/46 ,  H02M1/00 ,  H02M3/07

    摘要： A semiconductor device including a first internal voltage generating circuit that includes a capacitor including a first electrode and a second electrode, and the first internal voltage generating circuit to generate an internal voltage by charging the capacitor to a first voltage and applying a second voltage to the first electrode of the capacitor to generate a third voltage that is greater than the first and the second voltages on the second electrode in absolute value, and a control circuit to perform a control by applying a fourth voltage that is less than the first voltage to the capacitor when the first internal voltage generating circuit is in a standby state.

    Semiconductor device having plural memory chip
    6.
    发明授权
    Semiconductor device having plural memory chip 有权

    公开(公告)号：US10037971B2

    公开(公告)日：2018-07-31

    申请号：US15010930

    申请日：2016-01-29

    申请人： PS4 Luxco S.a.r.l.

    发明人： Akira Ide

    IPC分类号： G06F17/50 ,  H01L25/065 ,  H01L23/48 ,  G11C5/04 ,  H01L23/50 ,  G11C11/408

    CPC分类号： H01L25/0657 ,  G11C5/04 ,  G11C11/408 ,  H01L23/481 ,  H01L23/50 ,  H01L2224/16145 ,  H01L2225/06544

    摘要： A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

    Semiconductor device and manufacturing method therefor
    7.
    再颁专利
    Semiconductor device and manufacturing method therefor 有权

    公开(公告)号：USRE46798E1

    公开(公告)日：2018-04-17

    申请号：US14267201

    申请日：2014-05-01

    申请人： PS4 LUXCO S.A.R.L.

    发明人： Toshiyuki Hirota

    IPC分类号： H01L27/108 ,  H01L21/20 ,  H01L49/02 ,  H01L27/02

    CPC分类号： H01L28/60 ,  H01L27/0207 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    摘要： This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

    Semiconductor device verifying signal supplied from outside
    10.
    发明授权
    Semiconductor device verifying signal supplied from outside 有权
    从外部提供的半导体器件验证信号

    公开(公告)号：US09576641B2

    公开(公告)日：2017-02-21

    申请号：US14836315

    申请日：2015-08-26

    申请人： PS4 Luxco S.a.r.l.

    发明人： Chikara Kondo

    IPC分类号： G11C8/00 ,  G11C11/408 ,  G11C7/24 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/4063 ,  G11C11/409 ,  G11C8/12

    CPC分类号： G11C11/409 ,  G11C7/24 ,  G11C8/12 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/52

    摘要： Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.

    摘要翻译： 这里公开了一种半导体器件，其包括基于验证结果信号和外部命令产生内部命令的访问控制电路。 外部命令指示访问控制电路访问第一电路的第一命令和允许访问控制电路不访问第一电路的第二命令中的至少一个，或者允许访问控制电路保持当前状态 第一个电路。 访问控制电路当验证结果信号指示第一逻辑电平时，基于外部命令生成内部命令。 当验证结果信号指示第二逻辑电平时，访问控制电路即使外部命令指示第一命令也生成与第二命令相对应的内部命令。