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34 条记录 (耗时 0.026 秒)

    Slab based modular building system
    1.
    发明申请
    Slab based modular building system 有权
    基于平板的模块化建筑系统

    公开(公告)号：US20100223867A1

    公开(公告)日：2010-09-09

    申请号：US12660858

    申请日：2010-03-05

    申请人： Robert Floyd Tuttle

    发明人： Robert Floyd Tuttle

    IPC分类号： E02D27/02 ,  E02D27/08 ,  E04B1/16

    CPC分类号： E02D27/02 ,  E04B1/10 ,  E04B1/4157

    摘要： Embodiments of a slab based building system implementing a modular grid are presented herein. The square or rectangular grid may incorporate a connection point with vertical adjustment means for providing precise location of the grid elements relative to each other. An edge form is adapted to attach to the grid system. Additional building elements, such as pre-fabricated walls may be attached at the connection points.

    摘要翻译： 本文给出了实现模块化网格的基于平板的建筑系统的实施例。 方形或矩形网格可以包括与垂直调整装置的连接点，以提供网格元件相对于彼此的精确定位。 边缘形式适于附接到网格系统。 附加的建筑构件，例如预制墙体可以在连接点处附接。

    Low Noise Coding for Digital Data Interface
    2.
    发明申请
    Low Noise Coding for Digital Data Interface 有权
    数字数据接口的低噪声编码

    公开(公告)号：US20080222390A1

    公开(公告)日：2008-09-11

    申请号：US11697041

    申请日：2007-04-05

    申请人： Marco Corsi ,  Robert Floyd Payne

    发明人： Marco Corsi ,  Robert Floyd Payne

    IPC分类号： G06F9/30

    CPC分类号： H03M9/00 ,  H04L25/14

    摘要： A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.

    摘要翻译： 数字数据接口系统包括被配置为在多条数据线上传输数据字的数据发送器。 数据字可以包括具有从最低位数到最高位数的位数顺序的多个数字数据位，具有较高噪声含量的最低有序位数和具有较高谐波含量的最高有序位数。 该系统还包括编码器，其被配置为将多个数字数据位排列为串行化数据集，以由数据发送器在多个数据线中的每一条数据线上发送，其中至少一个串行化数据组的连续数据位被匹配，使得位 其中较高谐波含量与较高噪声含量的比特匹配，以便基本上减轻数据字的噪声内容和谐波内容中的至少一个。

    Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control
    4.
    发明授权
    Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control 有权
    在具有集成终端和共模控制的接收机中观察内部时钟和控制信号的电路

    公开(公告)号：US07315182B2

    公开(公告)日：2008-01-01

    申请号：US10778455

    申请日：2004-02-13

    申请人： Robert Floyd Payne ,  Bhavesh G. Bhakta ,  Richard Simpson

    发明人： Robert Floyd Payne ,  Bhavesh G. Bhakta ,  Richard Simpson

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： G01S1/00

    摘要： A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.

    摘要翻译： 串行数据接收器电路包括一对差分输入节点和接收器电路以及耦合在差分输入节点之间的终端电路。 终端电路包括一个共模节点。 共模控制电路连接到共模节点，并且呈现基本为零的输出阻抗。 在这样做时，共模控制电路向终端电路的共模节点提供共模电压，其表现出基本上理想的共模信号的终止和差分输入节点上的可忽略的负载。 在另一方面，提供了选择电路，其在测试操作模式期间选择性地将单端或差分测试信号传送到差分输入节点。 选择电路有助于观察接收机电路内的信号。

    Method and apparatus for testing a serial transmitter circuit
    6.
    发明授权
    Method and apparatus for testing a serial transmitter circuit 有权
    用于测试串行发射机电路的方法和装置

    公开(公告)号：US06865222B1

    公开(公告)日：2005-03-08

    申请号：US09643499

    申请日：2000-08-22

    申请人： Robert Floyd Payne

    发明人： Robert Floyd Payne

    IPC分类号： H04B3/46 ,  H04L1/24

    CPC分类号： H04B3/46 ,  H04L1/24

    摘要： An integrated circuit (12) contains a serializing transmitter, including a phase locked loop (31) that supplies seven clocks (41) with different phases to a serializer circuit (32). The serializer circuit accepts 7-bit words at a parallel input (42), and outputs these words serially in an end-to-end manner on a twisted pair (17), as a clock signal. The serializer circuit also accepts 7-bit words on a further parallel input (43), and transmits them serially in an end-to-end manner on a twisted pair (18), as serialized data. The integrated circuit also includes a built-in self-test circuit (33), which can supply test information to the two parallel inputs of the serializer circuit, and which can monitor the two twisted pairs while the serializer circuit operates at high data rates typical of normal operation, in order to detect any errors introduced by the serializer circuit. The self-test circuit produces a single digital output (48) to indicate whether an error has been detected.

    摘要翻译： 集成电路（12）包含串行发送器，其包括向串行器电路（32）提供具有不同相位的七个时钟（41）的锁相环（31）。 串行器电路在并行输入（42）接受7位字，并以双绞线（17）的端对端方式串行输出这些字作为时钟信号。 串行器电路还在另一个并行输入（43）上接受7位字，并在双绞线（18）上以端对端的方式串行发送，作为串行数据。 集成电路还包括一个内置的自检电路（33），可以将测试信息提供给串行器电路的两个并行输入，并且可以在串行器电路以高数据速率工作时监视两个双绞线 的正常操作，以便检测串行器电路引入的任何错误。 自检电路产生单个数字输出（48）以指示是否检测到错误。

    Method and apparatus for conditioning feeder chains in commercial baking ovens
    7.
    发明授权
    Method and apparatus for conditioning feeder chains in commercial baking ovens 有权
    用于在商业烘烤炉中调节进料链的方法和装置

    公开(公告)号：US06591968B2

    公开(公告)日：2003-07-15

    申请号：US09949439

    申请日：2001-09-07

    申请人： Richard E. Snell ,  Robert Floyd Lanham

    发明人： Richard E. Snell ,  Robert Floyd Lanham

    IPC分类号： B65G4722

    CPC分类号： A21C9/08 ,  A21B1/48 ,  B65G45/08 ,  B65G2207/24

    摘要： An apparatus and method for conditioning conveyor chains in commercial ovens of the type having a continuous conveyor chain supported in a track for transporting bakery products through the oven. A portion of the conveyor chain and supporting track transits outside the heated baking area of the oven and an automatic chain lubricator is positioned along the portion of the track transiting outside the baking area of the oven. A fan for creating a flow of cooling air and at least one air duct are located outside the baking area. The duct receives one end cooling air from the fan and directs the cooling air on to the conveyor chain along the portion thereof located outside the heated baking area of the oven and upstream from the lubricator. Also, an air knife is disposed upstream of the lubricator and directed onto the chain to remove undesired debris, etc., therefrom.

    摘要翻译： 一种用于调节具有连续输送链的商业炉中的输送链的装置和方法，所述输送链支撑在轨道中，用于将焙烤产品运送通过烘箱。 输送链和支撑履带的一部分在烘箱的加热烘烤区域外部转移，并且自动链条润滑器沿轨道部分位于烤箱烘烤区域外部。 用于产生冷却空气流和至少一个风道的风扇位于烘烤区域的外部。 管道从风扇接收一端冷却空气，并将冷却空气沿着位于烘箱的加热烘烤区域外部并且位于润滑器上游的部分引导到输送链上。 此外，气刀设置在润滑器的上游并且被引导到链上以从其中去除不期望的碎屑等。

    Portable back traction device and method of use
    8.
    发明授权
    Portable back traction device and method of use 有权

    公开(公告)号：US10220251B2

    公开(公告)日：2019-03-05

    申请号：US15902852

    申请日：2018-02-22

    申请人： Robert Floyd Cullison

    发明人： Robert Floyd Cullison

    IPC分类号： A63B21/00 ,  A63B23/00 ,  A63B23/02

    摘要： A device that is used to extend the spine and put it in traction, that is portable and user friendly. The device in an embodiment is grasped by the handles on either side and then is pushed toward the lower leg and against the upper calves via vertical intermediary bar pushing the legs with a horizontal bar in one direction and the shoulders in the other. The described process stretching the spine and putting the back in traction for the purposes of pain relief and stretching of the back muscles. The device can be an inexpensive alternative to other devices, as well as, easier to use. The force placed on the device and therefore on the spine or back is controlled by the user as is the ability to stop quite quickly if pain were to arise, giving the user complete and instant control.

    Digital Error Correction in an Analog-to-Digital Converter
    9.
    发明申请
    Digital Error Correction in an Analog-to-Digital Converter 有权
    模数转换器中的数字纠错

    公开(公告)号：US20130106628A1

    公开(公告)日：2013-05-02

    申请号：US13282262

    申请日：2011-10-26

    申请人： John Earle Miller ,  Robert Floyd Payne

    发明人： John Earle Miller ,  Robert Floyd Payne

    IPC分类号： H03M1/38 ,  H03M1/06

    CPC分类号： H03M1/0687 ,  H03M1/167

    摘要： An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.

    摘要翻译： 提供数字纠错的模数转换器（ADC）功能。 并行ADC级同步计时，将模拟输入信号转换为数字字; 数字输出中的至少一个根据纠错码进行编码。 判决逻辑电路对由并行级的数字输出的级联组成的代码字进行解码，以导出数字输出，从该数字输出可以导出与模拟输入信号对应的数字输出字。 对于系统代码的情况，判决逻辑电路可以提供用于校正来自ADC级之一的数字输出的一个或多个位的状态的误差信号; 或者，判决逻辑电路可以直接解码码字以提供数字输出。 该架构可以应用于流水线ADC中的阶段。

    Systems and methods of performing duty cycle control
    10.
    发明授权
    Systems and methods of performing duty cycle control 有权
    执行占空比控制的系统和方法

    公开(公告)号：US06933759B1

    公开(公告)日：2005-08-23

    申请号：US10773554

    申请日：2004-02-05

    申请人： Lin Wu ,  Robert Floyd Payne ,  Paul Eric Landman ,  Woo Jin Kim

    发明人： Lin Wu ,  Robert Floyd Payne ,  Paul Eric Landman ,  Woo Jin Kim

    IPC分类号： H03K3/017 ,  H03K5/151 ,  H03K5/156

    CPC分类号： H03K5/151 ,  H03K5/1565

    摘要： The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled buffer 306 buffers the differential pair of square wave signals and provides the buffered signals to a feedback circuit 304 that measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffer 306 can also remove skew from the signals. In a transmitter 102, the buffered signals are also generally provided to a multiplexer 112 or encoder and in a receiver 106, the buffered signals are also generally provided to a sampling component 122.

    摘要翻译： 本发明通过执行占空比校正来促进串行通信。 占空比校正部件302根据一对调整信号对一对差分正弦信号进行占空比校正，结果产生差分的方波信号。 交叉耦合缓冲器306缓冲差分对的方波信号，并将缓冲的信号提供给测量信号的占空比的反馈电路304，并相应地产生一对调整信号。 缓冲器306还可以消除信号的偏斜。 在发射机102中，经缓冲的信号也通常提供给多路复用器112或编码器，而在接收机106中，缓冲信号也通常提供给采样组件122。