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公开(公告)号：US20130106628A1
公开(公告)日：2013-05-02
申请号：US13282262
申请日：2011-10-26
CPC分类号： H03M1/0687 , H03M1/167
摘要： An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.
摘要翻译： 提供数字纠错的模数转换器（ADC）功能。 并行ADC级同步计时，将模拟输入信号转换为数字字; 数字输出中的至少一个根据纠错码进行编码。 判决逻辑电路对由并行级的数字输出的级联组成的代码字进行解码，以导出数字输出，从该数字输出可以导出与模拟输入信号对应的数字输出字。 对于系统代码的情况，判决逻辑电路可以提供用于校正来自ADC级之一的数字输出的一个或多个位的状态的误差信号; 或者，判决逻辑电路可以直接解码码字以提供数字输出。 该架构可以应用于流水线ADC中的阶段。
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公开(公告)号：US08547257B2
公开(公告)日：2013-10-01
申请号：US13282262
申请日：2011-10-26
IPC分类号： H03M1/06
CPC分类号： H03M1/0687 , H03M1/167
摘要： An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.
摘要翻译： 提供数字纠错的模数转换器（ADC）功能。 并行ADC级同步计时，将模拟输入信号转换为数字字; 数字输出中的至少一个根据纠错码进行编码。 判决逻辑电路对包括来自并行级的数字输出的组合的代码字进行解码，以导出数字输出，从该数字输出可以导出与模拟输入信号对应的数字输出字。 对于系统代码的情况，判决逻辑电路可以提供用于校正来自ADC级之一的数字输出的一个或多个位的状态的误差信号; 或者，判决逻辑电路可以直接解码码字以提供数字输出。 该架构可以应用于流水线ADC中的阶段。
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公开(公告)号：US06933759B1
公开(公告)日：2005-08-23
申请号：US10773554
申请日：2004-02-05
申请人： Lin Wu , Robert Floyd Payne , Paul Eric Landman , Woo Jin Kim
发明人： Lin Wu , Robert Floyd Payne , Paul Eric Landman , Woo Jin Kim
CPC分类号： H03K5/151 , H03K5/1565
摘要： The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled buffer 306 buffers the differential pair of square wave signals and provides the buffered signals to a feedback circuit 304 that measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffer 306 can also remove skew from the signals. In a transmitter 102, the buffered signals are also generally provided to a multiplexer 112 or encoder and in a receiver 106, the buffered signals are also generally provided to a sampling component 122.
摘要翻译： 本发明通过执行占空比校正来促进串行通信。 占空比校正部件302根据一对调整信号对一对差分正弦信号进行占空比校正，结果产生差分的方波信号。 交叉耦合缓冲器306缓冲差分对的方波信号，并将缓冲的信号提供给测量信号的占空比的反馈电路304，并相应地产生一对调整信号。 缓冲器306还可以消除信号的偏斜。 在发射机102中，经缓冲的信号也通常提供给多路复用器112或编码器，而在接收机106中，缓冲信号也通常提供给采样组件122。
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4.发明授权Self-biased bipolar ring-oscillator phase-locked loops with wide tuning range 有权具有宽调谐范围的自偏置双极性环形振荡器锁相环公开(公告)号：US07746177B2
公开(公告)日：2010-06-29
申请号：US12163599
申请日：2008-06-27
申请人： Zhiheng Cao , Robert Floyd Payne
发明人： Zhiheng Cao , Robert Floyd Payne
CPC分类号： H03L7/0995 , H03L7/0895 , H03L7/0896 , H03L7/093
摘要： Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals.
摘要翻译： 公开了具有宽调谐范围的自偏置双极性环形振荡器锁相环。 在特定示例中，描述了提供锁相环的装置，包括压控振荡器（VCO）以提供具有频率的输出时钟信号，量化器，相位频率检测器以产生调整信号， 和电荷泵来修改控制电压。 示例VCO包括几个环形振荡器级，其中每个环形振荡器级包括几个增益级，以基于控制电压和几个对应的阈值电压的比较来提供多个输出电流。 示例量化器包括若干比较器，用于基于输出电流产生数字信号。 示例性电荷泵基于数字信号和调整信号来修改控制电压，并且包括若干开关元件，以根据数字信号增加或减少到电荷泵的电流。
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公开(公告)号：US08269528B2
公开(公告)日：2012-09-18
申请号：US12948757
申请日：2010-11-18
IPC分类号： G11C27/02
CPC分类号： H03M1/0624 , G11C27/02 , H03L7/0812 , H03M1/0836 , H03M1/1245
摘要： Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result.
摘要翻译： 本文公开的装置和方法用于补偿出现在模拟信号捕获电路的输入处的模拟信号的反相（例如，差分相位）之间的偏斜，所述模拟信号在诸如跟踪保持或采样保持电路 ADC或类似设备。 两个捕获时钟中的每一个用于捕获一个反相。 一个或多个延迟电路被配置为在与两个捕获时钟相关联的时钟转换之间产生差分延迟。 差分延迟与反相之间的输入偏差成比例。 因此相位在相域轴上的基本相同的点被采样。 实施例操作以产生相位采样同步性，从而降低由偏斜引起的共模信号分量的振幅。 可能导致线性增加和失真减少。
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6.发明申请SELF-BIASED BIPOLAR RING-OSCILLATOR PHASE-LOCKED LOOPS WITH WIDE TUNING RANGE 有权自调式双极环振荡器相位锁定带宽调谐范围公开(公告)号：US20090322431A1
公开(公告)日：2009-12-31
申请号：US12163599
申请日：2008-06-27
申请人： Zhiheng Cao , Robert Floyd Payne
发明人： Zhiheng Cao , Robert Floyd Payne
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0895 , H03L7/0896 , H03L7/093
摘要： Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals.
摘要翻译： 公开了具有宽调谐范围的自偏置双极性环形振荡器锁相环。 在特定示例中，描述了提供锁相环的装置，其包括压控振荡器（VCO）以提供具有频率的输出时钟信号，量化器，相位频率检测器以产生调整信号， 和电荷泵来修改控制电压。 示例VCO包括几个环形振荡器级，其中每个环形振荡器级包括几个增益级，以基于控制电压和几个对应的阈值电压的比较来提供多个输出电流。 示例量化器包括若干比较器，用于基于输出电流产生数字信号。 示例性电荷泵基于数字信号和调整信号来修改控制电压，并且包括若干开关元件，以根据数字信号增加或减少到电荷泵的电流。
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公开(公告)号：US07636875B2
公开(公告)日：2009-12-22
申请号：US11697041
申请日：2007-04-05
申请人： Marco Corsi , Robert Floyd Payne
发明人： Marco Corsi , Robert Floyd Payne
IPC分类号： G06F11/00
摘要： A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.
摘要翻译： 数字数据接口系统包括被配置为在多条数据线上传输数据字的数据发送器。 数据字可以包括具有从最低位数到最高位数的位数顺序的多个数字数据位，具有较高噪声含量的最低有序位数和具有较高谐波含量的最高有序位数。 该系统还包括编码器，其被配置为将多个数字数据位排列为串行化数据集，以由数据发送器在多个数据线中的每一条数据线上发送，其中至少一个串行化数据组的连续数据位被匹配，使得位 其中较高谐波含量与较高噪声含量的比特匹配，以便基本上减轻数据字的噪声内容和谐波内容中的至少一个。
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8.发明授权High speed early/late discrimination systems and methods for clock and data recovery receivers 有权高速早/晚鉴别系统和时钟和数据恢复接收机的方法公开(公告)号：US07376211B2
公开(公告)日：2008-05-20
申请号：US10766161
申请日：2004-01-28
IPC分类号： H04L7/00
CPC分类号： H04L7/033
摘要： The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention employs a differential analog circuit, using current steering logic, to process center and edge samples and identify an average operation of the clocks. The circuit can identify transitions between adjacent center/edge data samples and determine whether an identified transition is early or late for each bit in a set of consecutive bits of a received serial data stream.
摘要翻译： 本发明通过提供可用于检测和调整时钟的操作和定时的机制来促进串行数据流的时钟和数据恢复。 本发明采用使用电流控制逻辑的差分模拟电路来处理中心和边缘采样并且识别时钟的平均操作。 电路可以识别相邻中心/边缘数据样本之间的转变，并且确定所接收的串行数据流的连续位的集合中的每个位的识别转变是早还是晚。
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9.发明授权Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability 有权基于Interpolator的时钟和数据恢复（CDR）电路，具有数字可编程的BW和跟踪功能公开(公告)号：US07315596B2
公开(公告)日：2008-01-01
申请号：US10781099
申请日：2004-02-17
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H04L7/0025 , H04L7/0337
摘要： The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).
摘要翻译： 本发明通过提供一种机制来促进串行数据流（317,715）的时钟和数据恢复（330,716 / 718），该机制可用于以多数据速率维持基于内插器的CDR电路（300,700）的固定跟踪能力（例如， 800）。 本发明还提供了宽数据速率范围CDR电路（300,700），但是使用针对固定频率优化的内插器设计。 本发明采用在宽范围的时钟和数据速率（例如800）上工作的速率可编程分频器电路（606,656,706），以在固定的VCO时钟频率下提供各种相位校正步长（例如800）。 基于数据速率（614,667）手动地对示例性CDR电路（600,650,700）的分频器（606,656,706）和有限状态机（FSM）（612,662,712）进行编程。 或者，可以在使用频率检测电路（725）的CDR操作（即时运行）期间从恢复的串行数据流（718）检测数据速率，以自动编程分频器（706）和FSM（712）以提供 CDR电路以最近的基准时钟速率（716）运行。
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公开(公告)号：US06353343B1
公开(公告)日：2002-03-05
申请号：US09603236
申请日：2000-06-26
IPC分类号： H03F345
CPC分类号： H04L25/0272 , H04L25/028 , H04L25/03878
摘要： A digital differential receiver IC that rejects the inter-symbol interference (ISI) that is imposed upon differential digital signals when long runs of a digital state (0 or 1) are transmitted over long cables. The ISI-rejecting differential receiver IC is implemented in either bipolar technology (n-p-n or p-n-p) or in insulated gate FET technology (p-channel or n-channel). The primary differential pair of transistors is connected to a secondary differential pair of transistors through a filter network so that a high pass “shelf” filter transfer function exists between the differential input signals and the output signals. This transfer function mitigates ISI by reducing the gain for long runs of a digital state (low frequencies) and enhancing the gain for the state transition edges (high frequencies).
摘要翻译： 数字差分接收器IC，当数字状态（0或1）的长时间运行通过长电缆传输时，拒绝对差分数字信号施加的符号间干扰（ISI）。 ISI抑制差分接收器IC采用双极技术（n-p-n或p-n-p）或绝缘栅FET技术（p沟道或n沟道）实现。 主差分对晶体管通过滤波器网络连接到次级差分晶体管对，使得差分输入信号和输出信号之间存在高通“搁置”滤波器传递函数。 该传递函数通过减少长时间运行的数字状态（低频）并增强状态转换边缘（高频）的增益来减轻ISI。
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