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    CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF
    1.
    发明申请
    CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF 审中-公开
    电容结构及其制作方法

    公开(公告)号：US20140061855A1

    公开(公告)日：2014-03-06

    申请号：US13605983

    申请日：2012-09-06

    申请人： Chien-Li KUO ,  Kuei-Sheng WU ,  Ju-Bao ZHANG ,  Rui-Huang CHENG ,  Xing-Hua ZHANG ,  Hong LIAO

    发明人： Chien-Li KUO ,  Kuei-Sheng WU ,  Ju-Bao ZHANG ,  Rui-Huang CHENG ,  Xing-Hua ZHANG ,  Hong LIAO

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/75 ,  H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A capacitor structure includes a first conductive structure, a dielectric structure, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode. The first conductive structure is disposed over a substrate. The dielectric structure is disposed over the substrate and partially enclosing the first conductive structure. The dielectric structure has a trench. A first surface of the first conductive structure is exposed through the trench of the dielectric structure. The first capacitor electrode is disposed on a bottom and a sidewall of the trench. The first capacitor electrode is electrically contacted with the first surface of the first conductive structure. The capacitor dielectric layer is disposed on a surface of the first capacitor electrode. The second capacitor electrode is disposed on a surface of the capacitor dielectric layer and filled in the trench.

    摘要翻译： 电容器结构包括第一导电结构，电介质结构，第一电容器电极，电容器电介质层和第二电容器电极。 第一导电结构设置在衬底上。 电介质结构设置在衬底上并部分地包围第一导电结构。 电介质结构具有沟槽。 第一导电结构的第一表面通过电介质结构的沟槽暴露。 第一电容器电极设置在沟槽的底部和侧壁上。 第一电容器电极与第一导电结构的第一表面电接触。 电容器电介质层设置在第一电容器电极的表面上。 第二电容器电极设置在电容器介电层的表面上并填充在沟槽中。

    METHOD FOR MANUFACTURING INTEGRATED CIRCUIT AND SEMICONDUCTOR STRUCTURE OF INTEGRATED CIRCUIT
    4.
    发明申请
    METHOD FOR MANUFACTURING INTEGRATED CIRCUIT AND SEMICONDUCTOR STRUCTURE OF INTEGRATED CIRCUIT 审中-公开
    集成电路的集成电路和半导体结构的制造方法

    公开(公告)号：US20090166796A1

    公开(公告)日：2009-07-02

    申请号：US11968205

    申请日：2008-01-02

    申请人： Chi-Lu Yu ,  Rui-Huang Cheng ,  Chien-Ming Lin ,  Ruei-Hao Huang

    发明人： Chi-Lu Yu ,  Rui-Huang Cheng ,  Chien-Ming Lin ,  Ruei-Hao Huang

    IPC分类号： H01L21/425 ,  H01L29/36

    CPC分类号： H01L21/823807 ,  H01L21/266 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/1033

    摘要： A method for manufacturing an integrated circuit includes: performing ion implantation on a wafer to make a chip in the wafer have an original doping concentration; dividing the chip into a plurality of regions; and controlling at least one region of plurality of the regions to not have further ion implantation performed thereon, thereby making the region only have single ion implantation performed thereon utilize the original doping concentration as a doping concentration of N-wells or P-wells of transistors in the region. Additionally, the region corresponds to signal output circuits of the integrated circuit.

    摘要翻译： 一种用于制造集成电路的方法包括：在晶片上执行离子注入以使晶片中的芯片具有原始掺杂浓度; 将芯片分成多个区域; 并且控制多个区域中的至少一个区域不具有在其上执行的其它离子注入，从而使该区域仅进行单次离子注入，利用原始掺杂浓度作为晶体管的N阱或P阱的掺杂浓度 在该区域。 此外，该区域对应于集成电路的信号输出电路。

    Heterojunction bipolar transistor and manufacturing method making the same
    9.
    发明申请
    Heterojunction bipolar transistor and manufacturing method making the same 审中-公开
    异质结双极晶体管和制造方法相同

    公开(公告)号：US20050085035A1

    公开(公告)日：2005-04-21

    申请号：US10687648

    申请日：2003-10-20

    申请人： Chih-Chiang Shen ,  Chang-Jung Chu ,  Rui-Huang Cheng ,  Yong-Yin Chen ,  Norio Hayafuji ,  Chin-Kun Peng

    发明人： Chih-Chiang Shen ,  Chang-Jung Chu ,  Rui-Huang Cheng ,  Yong-Yin Chen ,  Norio Hayafuji ,  Chin-Kun Peng

    IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L29/739

    CPC分类号： H01L29/66318 ,  H01L29/7371

    摘要： A method for improving a performance of a heterojunction bipolar transistor is provided. The method includes steps of providing a substrate; forming a first at least one semiconductor layer on the substrate; forming a second at least one semiconductor layer on the first at least one semiconductor layer; and inserting a thermal treatment process within the second at least one semiconductor layer so as to improve a performance of the heterojuntion bipolar transistor. Furthermore, the thermal treatment process is performed at a temperature ranged from 300° C. to 800° C.

    摘要翻译： 提供了一种用于改善异质结双极晶体管的性能的方法。 该方法包括提供衬底的步骤; 在所述衬底上形成第一至少一个半导体层; 在所述第一至少一个半导体层上形成第二至少一个半导体层; 以及在所述第二至少一个半导体层内插入热处理工艺，以便提高所述异质双极晶体管的性能。 此外，热处理过程在300℃至800℃的温度下进行。