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公开(公告)号：US12229253B2
公开(公告)日：2025-02-18
申请号：US17340164
申请日：2021-06-07
Inventor： Asif Rashid Zargar , Gilles Eyzat , Charul Jain
IPC: G06F21/55
Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.
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公开(公告)号：US20250055492A1
公开(公告)日：2025-02-13
申请号：US18929262
申请日：2024-10-28
Inventor： Danika Perrin , Sandrine Nicolas
IPC: H04B1/16
Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
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公开(公告)号：US12174950B2
公开(公告)日：2024-12-24
申请号：US17644711
申请日：2021-12-16
Inventor： Diana Moisuc , Christophe Eichwald
Abstract: Method for detecting the linear extraction of information in a processor using an instruction pointer. The method includes monitoring the values of the instruction pointer, determining a number of consecutive increments incrementing the values of the instruction pointer by a constant amount, and generating a detection signal if the number is greater than or equal to a detection threshold.
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公开(公告)号：US12045378B2
公开(公告)日：2024-07-23
申请号：US17657212
申请日：2022-03-30
Inventor： Franck Albesa , Nicolas Anquet
CPC classification number: G06F21/79 , G06F21/602 , H04L9/0894 , H04L9/14
Abstract: The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.
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公开(公告)号：US12045377B2
公开(公告)日：2024-07-23
申请号：US17657020
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/32 , G06F9/4401 , G06F21/72 , H04L9/08
CPC classification number: G06F21/72 , G06F9/4401 , H04L9/0861
Abstract: The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.
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Patent Agency Ranking
公开(公告)号：US20240120638A1
公开(公告)日：2024-04-11
申请号：US18545106
申请日：2023-12-19
Applicant: STMicroelectronics (Alps) SAS
Inventor： Deborah COGONI
Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
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公开(公告)号：US20240077522A1
公开(公告)日：2024-03-07
申请号：US18355977
申请日：2023-07-20
Inventor： Christophe Lorin , Nathalie Dubois
IPC: G01R19/165 , G01R15/04
CPC classification number: G01R19/16576 , G01R15/04
Abstract: A voltage matching circuit receives a first voltage received by a connector, and outputs a second voltage. The second voltage is equal to the first voltage, if the first voltage is less than a threshold voltage. The second voltage is equal to the first voltage divided by a first factor, if the first voltage is greater than or equal to the threshold voltage.
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公开(公告)号：US11879909B2
公开(公告)日：2024-01-23
申请号：US17869301
申请日：2022-07-20
Inventor： Klodjan Bidaj , Benjamin Ardaillon , Lauriane Gateka
IPC: G01R31/00 , G01R31/26 , G01R31/28 , G01R1/02 , G01R1/04 , G01R1/067 , G01R1/073 , G01R1/18 , G01R1/24 , G01R1/28
CPC classification number: G01R1/0416 , G01R31/2808 , G01R31/2889
Abstract: A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.
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公开(公告)号：US11853241B2
公开(公告)日：2023-12-26
申请号：US18065475
申请日：2022-12-13
Inventor： Jawad Benhammadi , Sylvain Meyer
IPC: G06F13/24 , G06F13/16 , G06F21/85 , H03K19/20 , G06F1/3237
CPC classification number: G06F13/24 , G06F1/3237 , G06F13/1689 , G06F21/85 , H03K19/20
Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
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公开(公告)号：US20230384953A1
公开(公告)日：2023-11-30
申请号：US18318416
申请日：2023-05-16
Applicant: STMicroelectronics (Alps) SAS
Inventor： Jawad Benhammadi
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0604 , G06F3/0655 , G06F3/0679
Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.
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