公开(公告)号：US09035396B2

公开(公告)日：2015-05-19

申请号：US13240475

申请日：2011-09-22

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L27/14 ,  H01L29/76 ,  H01L21/3105 ,  H01L27/105 ,  H01L29/66

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

公开(公告)号：US08053845B2

公开(公告)日：2011-11-08

申请号：US12291211

申请日：2008-11-07

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L21/70

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

公开(公告)号：US07339242B2

公开(公告)日：2008-03-04

申请号：US11360112

申请日：2006-02-22

申请人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

发明人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.

摘要翻译： 在一个实施例中，存储器件包括具有单元有源区和外围有源区的半导体衬底。 包括位线接触插头，公共源极线，外围栅极互连接触插头和外围金属互连接触插头的插头通过相同的工艺由相同的导电层形成。 此外，包括位线，电池金属互连，外围栅极互连和直接连接到插塞的外围金属互连的金属互连可以通过相同的工艺由相同的金属层形成。 因此，诸如插头和金属互连之类的互连结构被简化，因此它们的形成过程被简化。

公开(公告)号：US20120318567A1

公开(公告)日：2012-12-20

申请号：US13495216

申请日：2012-06-13

申请人： Jong-Hyun PARK ,  Jee-Yong KIM ,  Joon-Hee LEE ,  Jai-Hyuk SONG ,  Sang-Youn JO

发明人： Jong-Hyun PARK ,  Jee-Yong KIM ,  Joon-Hee LEE ,  Jai-Hyuk SONG ,  Sang-Youn JO

IPC分类号： H05K1/11 ,  H05K1/02 ,  H05K1/09

CPC分类号： H01L23/522 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wiring structure includes a first plug extending through a first insulating interlayer on a substrate, a first wiring extending through a second insulating interlayer on the first insulating interlayer and the first wiring is electrically connected to the first plug, a diffusion barrier layer pattern on the first wiring and on the second insulating interlayer, a portion of the second insulating interlayer being free of being covered by the diffusion barrier layer pattern, a second plug extending through the diffusion barrier layer pattern, the second plug is in contact with the first wiring, and a second wiring electrically connected to the second plug.

摘要翻译： 布线结构包括延伸穿过基板上的第一绝缘夹层的第一插塞，延伸穿过第一绝缘夹层上的第二绝缘夹层的第一布线和第一布线电连接到第一插头，扩散阻挡层图案 第一布线并且在第二绝缘中间层上，第二绝缘中间层的一部分不被扩散阻挡层图案覆盖，延伸穿过扩散阻挡层图案的第二插塞，第二插塞与第一布线接触， 以及电连接到第二插头的第二布线。

公开(公告)号：US20120028435A1

公开(公告)日：2012-02-02

申请号：US13240475

申请日：2011-09-22

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

公开(公告)号：US07920021B2

公开(公告)日：2011-04-05

申请号：US12580299

申请日：2009-10-16

申请人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

发明人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

IPC分类号： H01L25/00

CPC分类号： G11C16/10

摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

摘要翻译： 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

公开(公告)号：US20100207690A1

公开(公告)日：2010-08-19

申请号：US12580299

申请日：2009-10-16

申请人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

发明人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

IPC分类号： H03H11/24 ,  H03F3/14

CPC分类号： G11C16/10

摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

摘要翻译： 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

公开(公告)号：US5750433A

公开(公告)日：1998-05-12

申请号：US748865

申请日：1996-11-14

申请人： Sang-youn Jo

发明人： Sang-youn Jo

IPC分类号： H01L21/66 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76224

摘要： Methods of forming electrically isolated active regions in semiconductor substrates include the steps of forming a plurality of trenches in a face of a semiconductor substrate to define an active region pedestal between first and second dummy region pedestals and then forming an electrically insulating layer on the active region and dummy region pedestals and in the trenches disposed therebetween. A mask is then patterned to expose a portion of the electrically insulating layer on the active region pedestal and then the exposed portion of the electrically insulating layer is etched so that a thickness of the electrically insulating layer on the active region pedestal is less than a thickness of the electrically insulating layer on the first and second dummy region pedestals. A step is then performed to planarize the electrically insulating layer to selectively expose the active region pedestal but not the first and second dummy region pedestals. This planarizing step also results in the formation of a uniform surface profile at the edges of the active region pedestal.

摘要翻译： 在半导体衬底中形成电绝缘的有源区的方法包括以下步骤：在半导体衬底的表面上形成多个沟槽，以在第一和第二虚拟区域基座之间限定有源区基座，然后在有源区上形成电绝缘层 和虚设区域基座，并设置在它们之间的沟槽中。 然后对掩模进行构图以暴露有源区基座上的电绝缘层的一部分，然后蚀刻电绝缘层的暴露部分，使得有源区基座上的电绝缘层的厚度小于厚度 在第一和第二虚拟区域基座上的电绝缘层。 然后执行步骤以使电绝缘层平坦化以选择性地暴露有源区基座，而不是第一和第二虚拟区基座。 该平坦化步骤还导致在有源区基座的边缘处形成均匀的表面轮廓。

公开(公告)号：US20060284242A1

公开(公告)日：2006-12-21

申请号：US11449036

申请日：2006-06-07

申请人： Sang-Youn Jo

发明人： Sang-Youn Jo

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： A non-volatile memory device includes a device isolation layer disposed on a semiconductor substrate to define an active region, a floating gate disposed on the active region including a flat portion and a wall portion extending upwardly from an edge of the flat portion, a tunnel insulator interposed between the floating gate and the active region and a control gate electrode crossing over the active region and covering an inner side of the floating gate and at least a part of an outer side of the floating gate. The non-volatile memory device further includes a blocking insulator interposed between the control gate electrode and the floating gate.

摘要翻译： 非易失性存储器件包括设置在半导体衬底上以限定有源区的器件隔离层，设置在有源区上的浮置栅，包括平坦部分和从平坦部分的边缘向上延伸的壁部分，隧道 介于浮置栅极和有源区域之间的绝缘体以及跨越有源区域并覆盖浮动栅极的内侧和浮动栅极的外侧的至少一部分的控制栅极电极。 非易失性存储器件还包括插入在控制栅极电极和浮动栅极之间的阻挡绝缘体。

公开(公告)号：US20060186485A1

公开(公告)日：2006-08-24

申请号：US11360112

申请日：2006-02-22

申请人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

发明人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.

摘要翻译： 在一个实施例中，存储器件包括具有单元有源区和外围有源区的半导体衬底。 包括位线接触插头，公共源极线，外围栅极互连接触插头和外围金属互连接触插头的插头通过相同的工艺由相同的导电层形成。 此外，包括位线，电池金属互连，外围栅极互连和直接连接到插塞的外围金属互连的金属互连可以通过相同的工艺由相同的金属层形成。 因此，诸如插头和金属互连之类的互连结构被简化，因此它们的形成过程被简化。