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62 条记录 (耗时 0.029 秒)

    Method of operating non-volatile memory device
    1.
    发明授权
    Method of operating non-volatile memory device 有权
    操作非易失性存储器件的方法

    公开(公告)号：US09349456B2

    公开(公告)日：2016-05-24

    申请号：US13483521

    申请日：2012-05-30

    申请人： Se Jun Kim ,  Hea Jong Yang

    发明人： Se Jun Kim ,  Hea Jong Yang

    IPC分类号： G11C16/06 ,  G11C16/34 ,  G11C16/16 ,  G11C16/04

    CPC分类号： G11C16/06 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3409

    摘要： A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word lines of the memory cell block.

    摘要翻译： 一种操作非易失性存储器件的方法包括擦除存储器单元块，将高于目标电平的第一漏极导通电压提供给存储器单元块的漏极选择线，并且通过提供一个 软编程电压到存储单元块的字线。

    Charge trap type non-volatile memory device and program method thereof
    3.
    发明授权
    Charge trap type non-volatile memory device and program method thereof 失效
    电荷陷阱型非易失性存储器件及其编程方法

    公开(公告)号：US07616496B2

    公开(公告)日：2009-11-10

    申请号：US11771632

    申请日：2007-06-29

    申请人： Eun Seok Choi ,  Se Jun Kim ,  Kyoung Hwan Park ,  Hyun Seung Yoo

    发明人： Eun Seok Choi ,  Se Jun Kim ,  Kyoung Hwan Park ,  Hyun Seung Yoo

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3454 ,  G11C16/0466

    摘要： A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.

    摘要翻译： 一种对电荷陷阱型非易失性存储器件进行编程的方法包括将程序脉冲施加到所选择的存储单元，向所选择的存储单元施加去除脉冲，以及将程序验证脉冲施加到存储单元。 电荷陷阱型非易失性存储器件包括具有电荷陷阱存储单元的存储单元阵列，以及用于向电荷陷阱存储单元提供去除脉冲的高电压发生器。

    NAND flash memory device and method of manufacturing the same
    4.
    发明授权
    NAND flash memory device and method of manufacturing the same 有权
    NAND闪存器件及其制造方法

    公开(公告)号：US07456466B2

    公开(公告)日：2008-11-25

    申请号：US11445770

    申请日：2006-06-02

    申请人： Jae Chul Om ,  Nam Kyeong Kim ,  Se Jun Kim

    发明人： Jae Chul Om ,  Nam Kyeong Kim ,  Se Jun Kim

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

    摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

    摘要翻译： 公开了NAND​​闪速存储器件及其制造方法。 源极和漏极选择晶体管栅极比半导体衬底的有源区域低。 源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。 因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。 因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

    Analog delay locked loop having duty cycle correction circuit
    5.
    发明授权
    Analog delay locked loop having duty cycle correction circuit 失效
    具有占空比校正电路的模拟延迟锁定环

    公开(公告)号：US07078949B2

    公开(公告)日：2006-07-18

    申请号：US10750243

    申请日：2003-12-31

    申请人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    发明人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814

    摘要： An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.

    摘要翻译： 模拟延迟锁定环路装置包括用于接收内部时钟信号的第一块和参考时钟信号，以产生正常的多相时钟信号对和虚拟多相时钟信号对; 以及第二块，用于接收参考时钟信号以产生具有基于正常多相时钟信号对和伪多相时钟信号对的校正占空比的延迟锁定内部时钟信号。

    Semiconductor memory device with reduced data access time
    6.
    发明授权
    Semiconductor memory device with reduced data access time 有权
    具有减少数据存取时间的半导体存储器件

    公开(公告)号：US06937535B2

    公开(公告)日：2005-08-30

    申请号：US10696144

    申请日：2003-10-28

    申请人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

    发明人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

    IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4097 ,  G11C7/00

    CPC分类号： G11C7/18 ,  G11C11/4087 ,  G11C11/4097

    摘要： A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

    摘要翻译： 存储器件包括连接到全局位线的至少两个单元块，用于响应于指令输出数据; 至少一个全局位线连接单元，用于在控制块的控制下选择性地将全局位线连接到每个单元块，一个全局位线连接单元被分配在两个单元块之间; 以及所述控制块，用于控制存储在每个单元块中的数据到全局位线的输出，并将全局位线的输出数据恢复到原始单元块或另一个单元块，该单元块根据是否响应于 从原始单元块或另一个单元块输出下一个指令。

    Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data
    7.
    发明授权
    Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data 有权
    能够以连续脉冲串模式访问数据而不管访问数据的位置如何的半导体存储器件

    公开(公告)号：US06930951B2

    公开(公告)日：2005-08-16

    申请号：US10744322

    申请日：2003-12-22

    申请人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    发明人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    IPC分类号： G11C8/08 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12

    CPC分类号： G11C7/1018

    摘要： There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address. The method for driving a semiconductor memory device includes the steps of: receiving a first row address corresponding to a command; activating a word line of a first bank corresponding to the first row address; activating a word line of a second bank corresponding to a second row address, in which the second row address is consecutive to the first row address; sequentially accessing the predetermined number of data among the N data in a plurality of unit cells corresponding to the word line of the first bank; and sequentially accessing the remaining data in a plurality of unit cells corresponding to a word line of the second bank.

    摘要翻译： 提供了一种半导体存储器件及其驱动方法，其能够以连续的突发模式访问数据，而不管访问数据的位置如何。 半导体存储器件包括：第一存储体，包括对应于第一行地址的第一字线; 以及包括对应于第二行地址的第二字线的第二存储体，其中所述第二行地址与所述第一行地址连续。 驱动半导体存储器件的方法包括以下步骤：接收与命令对应的第一行地址; 激活对应于第一行地址的第一存储体的字线; 激活对应于第二行地址的第二存储体的字线，其中第二行地址与第一行地址连续; 在对应于第一存储单元的字线的多个单位单元中，依次访问N个数据中的预定数量的数据; 并且依次访问与第二存储体的字线对应的多个单位单元中的剩余数据。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06757210B2

    公开(公告)日：2004-06-29

    申请号：US10330892

    申请日：2002-12-27

    申请人： Sang Hoon Hong ,  Se Jun Kim ,  Jeong Hoon Kook

    发明人： Sang Hoon Hong ,  Se Jun Kim ,  Jeong Hoon Kook

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/10 ,  G11C2207/002

    摘要： A semiconductor memory device configured to share a local I/O line is described herein. The device includes: a memory cell array including a plurality of memory cells; a plurality of bit line sense amplifiers configured to sense and to amplify data stored in the plurality of memory cells; a plurality of bit lines configured to transmit transmitting the data stored in the plurality of memory cells to the plurality of bit line sense amplifiers, respectively; a plurality of bit line dividing circuits configured to selectively divide the plurality of bit lines; and a plurality of column selecting circuits configured to sequentially transmit the data amplified by the plurality of bit line sense amplifiers to corresponding I/O lines.

    摘要翻译： 这里描述了配置成共享本地I / O线的半导体存储器件。 该装置包括：包括多个存储单元的存储单元阵列; 多个位线读出放大器，被配置为感测和放大存储在所述多个存储器单元中的数据; 多个位线，被配置为分别将多个存储单元中存储的数据发送到多个位线读出放大器; 多个位线分割电路，被配置为选择性地划分所述多个位线; 以及多个列选择电路，被配置为顺序地将由多个位线读出放大器放大的数据发送到对应的I / O线。

    NAND flash memory device and method of manufacturing the same
    10.
    发明授权
    NAND flash memory device and method of manufacturing the same 有权
    NAND闪存器件及其制造方法

    公开(公告)号：US08268685B2

    公开(公告)日：2012-09-18

    申请号：US13069273

    申请日：2011-03-22

    申请人： Jae Chul Om ,  Nam Kyeong Kim ,  Se Jun Kim

    发明人： Jae Chul Om ,  Nam Kyeong Kim ,  Se Jun Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

    摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

    摘要翻译： 公开了NAND​​闪速存储器件及其制造方法。 源极和漏极选择晶体管栅极比半导体衬底的有源区域低。 源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。 因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。 因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。