公开(公告)号：US08076720B2

公开(公告)日：2011-12-13

申请号：US12447817

申请日：2008-09-26

申请人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

发明人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66734 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813

摘要： The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.

摘要翻译： 本发明提供了一种沟槽栅型晶体管，其中栅极漏电流被防止并且栅极电容减小。 在N型半导体层中形成沟槽。 在沟槽中的晶体管的有源区域的N型半导体层的区域上形成薄的氧化硅膜。 另一方面，在不是有源区的区域上形成比氧化硅膜厚的氧化硅膜。 此外，从沟槽内部延伸到其外部的引导部分形成与氧化硅膜接触的栅电极。 这提供了在前导部分的栅电极和N-型半导体层的角部之间的长距离，从而防止栅极漏电流并降低栅极电容。

公开(公告)号：US08022475B2

公开(公告)日：2011-09-20

申请号：US12434128

申请日：2009-05-01

申请人： Yasuhiro Takeda ,  Seiji Otake ,  Kazunori Fujita

发明人： Yasuhiro Takeda ,  Seiji Otake ,  Kazunori Fujita

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/823456 ,  H01L21/2815 ,  H01L21/823412 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7813

摘要： An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer. The trench gate type transistor is formed in the first region of the semiconductor layer and the planar type transistor is formed in the second region of the semiconductor layer.

摘要翻译： 同时优化沟槽栅型晶体管的导通电阻和平面型晶体管的耐电压。 半导体层的第一和第二区域中的每一个分别通过在半导体衬底的第一和第二区域中的每一个上外延生长而形成。 在半导体衬底的第一区域和半导体层的第一区域之间形成第一掩埋层，而在半导体衬底的第二区域和半导体层的第二区域之间形成第二掩埋层。 第一掩埋层由N +型第一杂质掺杂层和延伸超过第一杂质掺杂层的N型第二杂质掺杂层形成。 第二掩埋层仅由N +型杂质掺杂层形成。 在半导体层的第一区域中，杂质从半导体层的表面扩散到半导体层中以形成N型第三杂质掺杂层。 沟槽栅型晶体管形成在半导体层的第一区域中，并且平面型晶体管形成在半导体层的第二区域中。

公开(公告)号：US07968941B2

公开(公告)日：2011-06-28

申请号：US12412659

申请日：2009-03-27

申请人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

发明人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681

摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.

摘要翻译： 半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。 主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。 栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分 方向。

公开(公告)号：US20100301411A1

公开(公告)日：2010-12-02

申请号：US12787052

申请日：2010-05-25

申请人： Yasuhiro TAKEDA ,  Kazunori Fujita ,  Haruki Yoneda

发明人： Yasuhiro TAKEDA ,  Kazunori Fujita ,  Haruki Yoneda

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7823

摘要： The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.

摘要翻译： 本发明防止DMOS晶体管的源极 - 漏极击穿电压由于在围绕栅极宽度端部的场氧化物膜角部附近的有源区域中形成的具有高浓度的N型漂移层的部分中的电介质击穿而减小。 通过在栅极宽度端部的外侧形成更宽的有源区域，将场氧化膜角部设置在栅极宽度端部的外侧，以便进一步远离形成在栅极宽度端部的P型主体层 部分比在门宽中心部分。 由此，在场氧化膜角部附近具有高浓度的N型漂移层配置为远离P型体层而不增加器件面积。

公开(公告)号：US20090242981A1

公开(公告)日：2009-10-01

申请号：US12412659

申请日：2009-03-27

申请人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

发明人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681

摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.

摘要翻译： 半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。 主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。 栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分 方向。

公开(公告)号：US07273810B2

公开(公告)日：2007-09-25

申请号：US10950689

申请日：2004-09-28

申请人： Yohko Naruse ,  Naoteru Matsubara ,  Kazunori Fujita

发明人： Yohko Naruse ,  Naoteru Matsubara ,  Kazunori Fujita

IPC分类号： H01L21/44 ,  H01L29/40

CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus is constructed such that the top surface, contacting a barrier metal film, of a conducting film embedded in a trench is located below the top surface of a second interlayer insulating film. The semiconductor apparatus is fabricated such that a plasma treatment is performed in a non-nitriding environment after a polishing process using CMP, so as to form a damaged layer on top of the second interlayer insulating film and the conducting film, and a portion of the damaged layer is removed by etching.

摘要翻译： 构造半导体装置，使得嵌入沟槽中的导电膜的与阻挡金属膜接触的顶表面位于第二层间绝缘膜的顶表面下方。 制造半导体装置，使得在使用CMP的抛光处理之后在非氮化环境中进行等离子体处理，以在第二层间绝缘膜和导电膜的顶部上形成损伤层，并且部分 损伤层通过蚀刻去除。

公开(公告)号：US4550067A

公开(公告)日：1985-10-29

申请号：US622624

申请日：1984-06-20

申请人： Tatsuo Horiba ,  Kazunori Fujita ,  Shinpei Matsuda ,  Kohki Tamura

发明人： Tatsuo Horiba ,  Kazunori Fujita ,  Shinpei Matsuda ,  Kohki Tamura

IPC分类号： H01M4/60 ,  H01M6/16 ,  H01M10/05 ,  H01M10/052 ,  H01M10/0568 ,  H01M10/00

CPC分类号： H01M10/05 ,  H01M4/60 ,  H01M6/166

摘要： The disclosure is concerned with a secondary cell comprising a positive electrode, a negative electrode, a liquidous electrolyte layer interposed between the electrodes, said electrolyte containing a dopant consisting of an anion and a cation, means for electrically insulating the electrodes, and an envelope for enclosing and for air-tightly sealing the electrodes and the electrolyte.The positive electrode or the negative electrode is made of a material, such as, phthalocyanine complexes, metal porphyrin complexes, chalcogenides of transition metals and an electrically conductive polymeric material such as polyacetylene.The secondary cell of the present invention has a long service life because of its good durability to charge and discharge operations.

摘要翻译： 本发明涉及一种二次电池，其包括正电极，负电极，介于电极之间的液态电解质层，所述电解质含有由阴离子和阳离子组成的掺杂剂，用于电绝缘电极的装置，以及用于 封闭并气密地密封电极和电解质。 正极或负极由诸如酞菁络合物，金属卟啉络合物，过渡金属的硫族化合物和导电聚合材料如聚乙炔的材料制成。 本发明的二次电池由于其对充放电操作的良好的耐久性而具有长的使用寿命。

公开(公告)号：US4537278A

公开(公告)日：1985-08-27

申请号：US658214

申请日：1984-10-05

申请人： Makoto Okada ,  Kazunori Fujita

发明人： Makoto Okada ,  Kazunori Fujita

IPC分类号： F01N1/08 ,  F01N1/24 ,  F01N13/08 ,  F01N7/08

CPC分类号： F01N13/08 ,  F01N1/082 ,  F01N1/24 ,  F01N2240/20

摘要： An exhaust duct connector takes the form of a Y-shaped passage. Both of the branches of the Y are adapted to receive ends of upstream exhaust ducts and a leg of the Y is adapted to receive one end of a downstream exhaust duct. A substantially plate-like partition is positioned at the junction of the Y parallel to the single leg. The partition includes a plurality of holes through which exhaust can pass. The partition may include an outer partition member having a plurality of holes and an inner partition having numerous extremely small holes covered by the outer partition member. The partition may contact the adjacent inside wall of the Y-shaped passage, or be spaced from the adjacent inside wall of the Y-shaped passage. The partition may take the form of an airfoil.

摘要翻译： 排气管连接器呈Y形通道的形式。 Y的两个分支适于接收上游排气管的端部，并且Y的腿适于接纳下游排气管的一端。 基本上板状的隔板位于Y平行于单腿的接合处。 分隔件包括排气可以通过的多个孔。 分隔件可以包括具有多个孔的外分隔构件和具有由外分隔构件覆盖的许多极小孔的内分隔件。 分隔件可以与Y形通道的相邻内壁接触，或者与Y形通道的相邻内壁间隔开。 分隔件可以采取翼型的形式。

公开(公告)号：US4070284A

公开(公告)日：1978-01-24

申请号：US673529

申请日：1976-04-05

申请人： Kazunori Fujita ,  Seiji Takeuchi ,  Yoshinori Takata ,  Mamoru Taki ,  Yoshimasa Hamano

发明人： Kazunori Fujita ,  Seiji Takeuchi ,  Yoshinori Takata ,  Mamoru Taki ,  Yoshimasa Hamano

IPC分类号： B01D15/08 ,  G01N30/08 ,  G01N30/46 ,  G01N30/60 ,  G01N30/88

CPC分类号： G01N30/08 ,  B01D15/08 ,  B01D15/12 ,  B01D15/361 ,  G01N2030/085 ,  G01N2030/8881 ,  G01N30/461 ,  G01N30/468 ,  G01N30/6004 ,  G01N30/6017

摘要： A definite, but large amount of a sample solution is fed to a small concentration column filled with a packing material to retain in the concentration column components to be measured in the sample solution. Then, a small amount of a desorbing solution is fed to the concentration column to desorb the components retained in the concentration column. The effluent solution containing the desorbed components is fed to a separation column filled with a packing material. An eluting solution is fed to the separation column to separate the components from one another, and the components are detected by a detector.Since the components are separated from one another after their concentrations have been elevated, and thus the components can be measured with a high sensitivity.

摘要翻译： 将一定量但大量的样品溶液供给到填充有填充材料的小浓度柱，以将样品溶液中待测量的浓度列保留在组分中。 然后，将少量解吸溶液加入到浓缩塔中以解吸保留在浓缩塔中的组分。 含有脱附组分的流出液被加入填充有填料的分离塔中。 将洗脱溶液进料到分离塔以将组分彼此分离，并通过检测器检测组分。

公开(公告)号：US08525259B2

公开(公告)日：2013-09-03

申请号：US12787052

申请日：2010-05-25

申请人： Yasuhiro Takeda ,  Kazunori Fujita ,  Haruki Yoneda

发明人： Yasuhiro Takeda ,  Kazunori Fujita ,  Haruki Yoneda

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7823

摘要： The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.

摘要翻译： 本发明防止DMOS晶体管的源极 - 漏极击穿电压由于在围绕栅极宽度端部的场氧化物膜角部附近的有源区域中形成的具有高浓度的N型漂移层的部分中的电介质击穿而减小。 通过在栅极宽度端部的外侧形成更宽的有源区域，将场氧化膜角部设置在栅极宽度端部的外侧，以便进一步远离形成在栅极宽度端部的P型主体层 部分比在门宽中心部分。 由此，在场氧化膜角部附近具有高浓度的N型漂移层配置为远离P型体层而不增加器件面积。