公开(公告)号：US08022475B2

公开(公告)日：2011-09-20

申请号：US12434128

申请日：2009-05-01

申请人： Yasuhiro Takeda ,  Seiji Otake ,  Kazunori Fujita

发明人： Yasuhiro Takeda ,  Seiji Otake ,  Kazunori Fujita

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/823456 ,  H01L21/2815 ,  H01L21/823412 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7813

摘要： An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer. The trench gate type transistor is formed in the first region of the semiconductor layer and the planar type transistor is formed in the second region of the semiconductor layer.

摘要翻译： 同时优化沟槽栅型晶体管的导通电阻和平面型晶体管的耐电压。 半导体层的第一和第二区域中的每一个分别通过在半导体衬底的第一和第二区域中的每一个上外延生长而形成。 在半导体衬底的第一区域和半导体层的第一区域之间形成第一掩埋层，而在半导体衬底的第二区域和半导体层的第二区域之间形成第二掩埋层。 第一掩埋层由N +型第一杂质掺杂层和延伸超过第一杂质掺杂层的N型第二杂质掺杂层形成。 第二掩埋层仅由N +型杂质掺杂层形成。 在半导体层的第一区域中，杂质从半导体层的表面扩散到半导体层中以形成N型第三杂质掺杂层。 沟槽栅型晶体管形成在半导体层的第一区域中，并且平面型晶体管形成在半导体层的第二区域中。

公开(公告)号：US08916931B2

公开(公告)日：2014-12-23

申请号：US13286832

申请日：2011-11-01

申请人： Yasuhiro Takeda ,  Seiji Otake

发明人： Yasuhiro Takeda ,  Seiji Otake

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7823 ,  H01L29/7835

摘要： An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.

摘要翻译： 由形成有N +型漏极层等的N型外延层构成的N型层由从N型外延层的前表面延伸到N +型掩埋层的P型漏极隔离层包围。 在由P型漏极隔离层包围的N型外延层构成的N型层和从N型层的前表面延伸到内部的P型元件隔离层形成P型集电极层。 因此，形成使用第一导电型漏极隔离层作为发射极，第二导电型N型层作为基极的集电极层作为集电极的寄生双极型晶体管，以将浪涌电流流入地线。

公开(公告)号：US20100193865A1

公开(公告)日：2010-08-05

申请号：US12680012

申请日：2008-09-26

申请人： Yasuhiro Takeda ,  Seiji Otake ,  Shuichi Kikuchi

发明人： Yasuhiro Takeda ,  Seiji Otake ,  Shuichi Kikuchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0696 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/7816

摘要： The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A′. A first body layer 17A′ is formed by this first ion implantation. The first body layer 17A′ is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A′ in the first corner portion 14C1 is higher than that of a conventional transistor.

摘要翻译： 本发明提供了一种DMOS晶体管，其中当通过倾斜离子注入形成体层时，泄漏电流降低，并且处于断开状态的晶体管的源极 - 漏极击穿电压增强。 在形成光致抗蚀剂层18之后，使用光致抗蚀剂层18和栅电极14作为掩模，在栅极电极14的内侧沿箭头A所示的第一方向进行第一离子注入 '。 通过该第一离子注入形成第一体层17A'。 第一主体层17A'形成为从第一角部14C1延伸到栅极14的下方，第一角部14C1中的主体层17A'的P型杂质浓度高于 常规晶体管。

公开(公告)号：US07768067B2

公开(公告)日：2010-08-03

申请号：US12425592

申请日：2009-04-17

申请人： Seiji Otake ,  Shuichi Kikuchi ,  Yasuhiro Takeda ,  Kenichi Maki

发明人： Seiji Otake ,  Shuichi Kikuchi ,  Yasuhiro Takeda ,  Kenichi Maki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689

摘要： This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.

摘要翻译： 本发明提供一种DMOS晶体管，其具有降低的导通电阻并且防止其相对静电放电的强度劣化。 DMOS晶体管的源极层的边缘部分被设置为从栅电极的内角部分退出。 硅化物层被构造为不从源极层的边缘部分延伸出来。 也就是说，尽管在源极层的表面上形成硅化物层，但是在源极层和栅电极的内角部之间露出的体层的一部分的表面上不形成硅化物层 。 结果，由于电流几乎均匀地流过整个DMOS晶体管而没有会聚，所以可以提高抵抗静电放电的强度。

公开(公告)号：US08754479B2

公开(公告)日：2014-06-17

申请号：US13612194

申请日：2012-09-12

申请人： Seiji Otake ,  Yasuhiro Takeda ,  Yuta Miyamoto

发明人： Seiji Otake ,  Yasuhiro Takeda ,  Yuta Miyamoto

IPC分类号： H01L27/06

CPC分类号： H01L27/0259

摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.

摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和P +型掩埋层的PN结二极管和使用连接到P +型扩散层的P +型绘图层的寄生PNP双极晶体管形成，作为 作为基极的N型外延层和作为集电体的P型半导体基板。 P +型埋层与阳极连接，P +型扩散层与P +型扩散层连接并围绕P +型扩散层的N +型扩散层与阴极电极连接。 当向阴极施加大的正静电时，寄生PNP双极晶体管导通以流过大的放电电流。

公开(公告)号：US08395210B2

公开(公告)日：2013-03-12

申请号：US12680012

申请日：2008-09-26

申请人： Yasuhiro Takeda ,  Seiji Otake ,  Shuichi Kikuchi

发明人： Yasuhiro Takeda ,  Seiji Otake ,  Shuichi Kikuchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0696 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/7816

摘要： The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A′. A first body layer 17A′ is formed by this first ion implantation. The first body layer 17A′ is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A′ in the first corner portion 14C1 is higher than that of a conventional transistor.

摘要翻译： 本发明提供了一种DMOS晶体管，其中当通过倾斜离子注入形成体层时，泄漏电流降低，并且处于断开状态的晶体管的源极 - 漏极击穿电压增强。 在形成光致抗蚀剂层18之后，使用光致抗蚀剂层18和栅电极14作为掩模，在栅极电极14的内侧沿箭头A所示的第一方向进行第一离子注入 '。 通过该第一离子注入形成第一体层17A'。 第一主体层17A'形成为从第一角部14C1延伸到栅极14的下方，第一角部14C1中的主体层17A'的P型杂质浓度高于 常规晶体管。

公开(公告)号：US07948031B2

公开(公告)日：2011-05-24

申请号：US12167764

申请日：2008-07-03

申请人： Seiji Otake ,  Yasuhiro Takeda ,  Kenichi Maki

发明人： Seiji Otake ,  Yasuhiro Takeda ,  Kenichi Maki

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7809

摘要： A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.

摘要翻译： 一种半导体器件包括：栅极，其形成在沟槽中，绝缘膜具有与源极区域和基极区域相邻的第一侧面;以及第二导电型第一杂质区域，其形成在所述沟槽的第二侧面附近， 凹槽和存在于基底区域下方的漏区的引出部分，以便向下延伸超过凹槽的下端。

公开(公告)号：US20090197378A1

公开(公告)日：2009-08-06

申请号：US12363553

申请日：2009-01-30

申请人： Satoru Shimada ,  Yasuhiro Takeda ,  Seiji Otake

发明人： Satoru Shimada ,  Yasuhiro Takeda ,  Seiji Otake

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region.

摘要翻译： 一种制造半导体器件的方法包括：形成缺陷抑制膜的第一步骤，其抑制由于在半导体衬底上注入杂质引起的缺陷的增加;第二步骤，通过注入在半导体衬底的表面上形成有源区 通过缺陷抑制膜的杂质，除去缺陷抑制膜的第三步骤，以及形成界面状态抑制膜抑制活性区域上的有源区的界面态密度增加的第四步骤。

公开(公告)号：US20070166925A1

公开(公告)日：2007-07-19

申请号：US11617517

申请日：2006-12-28

申请人： Yasuhiro Takeda ,  Mitsuaki Morigami ,  Satoru Shimada ,  Kazuhiro Yoshitake ,  Shuichi Kikuchi ,  Seiji Otake ,  Toshiyuki Ohkoda

发明人： Yasuhiro Takeda ,  Mitsuaki Morigami ,  Satoru Shimada ,  Kazuhiro Yoshitake ,  Shuichi Kikuchi ,  Seiji Otake ,  Toshiyuki Ohkoda

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7809 ,  H01L21/743 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/781

摘要： A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

摘要翻译： 半导体器件包括在半导体衬底的表面中形成的沟槽。 导体嵌入在沟槽中。 导电层被布置成与半导体衬底的表面上的沟槽相邻。 包括由导体和导电层之一提供的源和由导体和导电层中的另一个提供的漏极的半导体元件形成在半导体元件形成区域中。 在整个半导体元件形成区域的半导体衬底内嵌有平面布线层，并与导体连接。

公开(公告)号：US08618584B2

公开(公告)日：2013-12-31

申请号：US13612224

申请日：2012-09-12

申请人： Seiji Otake ,  Yasuhiro Takeda ,  Yuta Miyamoto

发明人： Seiji Otake ,  Yasuhiro Takeda ,  Yuta Miyamoto

IPC分类号： H01L21/70 ,  H01L23/62

CPC分类号： H01L27/0259

摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.

摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和第一P +型掩埋层的PN结二极管和使用连接到P +型扩散层的第二P +型掩埋层的寄生PNP双极晶体管形成 作为发射极，以N型外延层为基底，第一P +型埋层作为集电体。 第一P +型埋层与阳极连接，P +型扩散层和围绕P +型扩散层的N +型扩散层与阴极电极连接。 当向阴极施加大的正静电时，并且寄生PNP双极晶体管导通以流过大的放电电流。