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    Methods of fabricating high voltage devices
    2.
    发明申请
    Methods of fabricating high voltage devices 有权
    制造高压器件的方法

    公开(公告)号：US20060286741A1

    公开(公告)日：2006-12-21

    申请号：US11154431

    申请日：2005-06-16

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/0629 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

    摘要： Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

    摘要翻译： 制造方法和器件包括在电容器形成期间形成的场板。 在半导体衬底中形成隔离结构。 在半导体衬底中形成阱区。 在阱区域中形成漏极延伸区域。 在器件上形成栅极电介质层。 形成用作栅电极和底电容器板的栅极电极层。 对栅极电极和栅极介电层进行图案化以形成栅极结构。 源区和漏区形成在阱区和漏极延伸区内。 形成也用作电容器电介质的硅化物阻挡层。 在阻挡层上形成场板和顶部电容器板。

    Drain extended PMOS transistor with increased breakdown voltage
    3.
    发明申请
    Drain extended PMOS transistor with increased breakdown voltage 有权
    以增加的击穿电压漏极扩展PMOS晶体管

    公开(公告)号：US20060170056A1

    公开(公告)日：2006-08-03

    申请号：US11047418

    申请日：2005-01-31

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

    IPC分类号： H01L29/76

    CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.

    摘要翻译： 提供了包括漏极延伸PMOS晶体管（CT1a）的半导体器件（102），以及制造方法（202）。 在形成PMOS晶体管时，晶体管的漏极（124）形成在p型上部外延层（106）的区域（125）上，其中p型上部外延层（106）的区域（125） ）夹在形成在p型上部外延层（106）内的左P-WELL区域（130a）和右P-WELL区域（130b）之间。 p型上部外延层（106）形成在其上形成有n埋层（108）的半导体本体（104）上。 这种布置用于增加漏极延伸PMOS晶体管的击穿电压（BVdss）。

    Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
    5.
    发明申请
    Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof 有权
    非均匀掺杂高压漏极延迟晶体管及其制造方法

    公开(公告)号：US20050253217A1

    公开(公告)日：2005-11-17

    申请号：US10832009

    申请日：2004-04-26

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

    IPC分类号： H01L21/8234 ,  H01L21/266 ,  H01L21/336 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L27/0623 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2029/42388

    摘要： The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

    摘要翻译： 本发明在一个实施例中提供一种晶体管（100）。 晶体管（100）包括半导体衬底（105）上方的掺杂半导体衬底（105）和栅极结构（110），栅极结构（110）具有栅极拐角（125）。 晶体管（100）还包括由掺杂半导体衬底（105）围绕的漏极扩展阱（115）。 漏极扩展阱（115）具有与掺杂半导体衬底（105）相反的掺杂剂类型。 漏极扩展阱（115）还在高掺杂区域（150）之间具有低掺杂区域（145），其中低掺杂区域（155）的边缘基本上与由 门角（125）。 本发明的其他实施例包括制造晶体管（200）和集成电路（300）的方法。

    Method and apparatus for drying materials including veneers
    7.
    发明申请
    Method and apparatus for drying materials including veneers 失效
    用于干燥材料的方法和装置，包括单板

    公开(公告)号：US20050217136A1

    公开(公告)日：2005-10-06

    申请号：US11088226

    申请日：2005-03-23

    申请人： Timothy Blankenship ,  Junius Himes ,  Brent Lillesand ,  James Todd ,  Edward Constantine

    发明人： Timothy Blankenship ,  Junius Himes ,  Brent Lillesand ,  James Todd ,  Edward Constantine

    IPC分类号： F26B5/04 ,  F26B9/06 ,  F26B13/30

    CPC分类号： F26B5/048 ,  F26B5/045 ,  F26B9/066 ,  F26B2210/14

    摘要： An apparatus and method is provided to dry veneer or other items by vaporization of moisture in the item. Apparatus has an insulated chamber with a frame and a drawer with a door. A mesh surface of the drawer supports item for drying with a heater at sub-atmospheric pressure inside of the chamber. Item is placed on the layer of mesh of the drawer of the apparatus and secured with fasteners such as another layer of mesh. The drawer with fastened item is placed into the chamber of the apparatus. With the drawer fully engaged within the chamber, the drying apparatus is closed with an airtight seal. A pump draws a vacuum in the chamber and heat is directed at the item to raise the temperature of the item to less than 160° F., particularly between 120° F. to 150° F. Apparatus can dry veneer in less than five minutes.

    摘要翻译： 提供了一种装置和方法，用于通过物品中的水分蒸发来干燥胶合板或其它物品。 设备具有带框架的绝缘室和带门的抽屉。 抽屉的网眼表面支撑用于在室内的低于大气压的加热器干燥的物品。 将物品放置在设备的抽屉的网格层上，并用诸如另一层网的紧固件固定。 带有紧固件的抽屉放置在设备的室内。 当抽屉完全接合在室内时，干燥装置用气密密封封闭。 泵在室内抽真空，热量指向物品，以将物品的温度升高至小于160°F，特别是120°F至150°F。设备可在不到五分钟内干燥单板 。

    Method for drying veneers
    10.
    发明授权
    Method for drying veneers 失效
    干燥单板的方法

    公开(公告)号：US07383643B2

    公开(公告)日：2008-06-10

    申请号：US11088226

    申请日：2005-03-23

    申请人： Timothy Blankenship ,  Junius Himes ,  Brent Lillesand ,  James Todd ,  Edward Constantine

    发明人： Timothy Blankenship ,  Junius Himes ,  Brent Lillesand ,  James Todd ,  Edward Constantine

    IPC分类号： F26B5/04

    CPC分类号： F26B5/048 ,  F26B5/045 ,  F26B9/066 ,  F26B2210/14

    摘要： An apparatus and method is provided to dry veneer or other items by vaporization of moisture in the item. Apparatus has an insulated chamber with a frame and a drawer with a door. A mesh surface of the drawer supports item for drying with a heater at sub-atmospheric pressure inside of the chamber. Item is placed on the layer of mesh of the drawer of the apparatus and secured with fasteners such as another layer of mesh. The drawer with fastened item is placed into the chamber of the apparatus. With the drawer fully engaged within the chamber, the drying apparatus is closed with an airtight seal. A pump draws a vacuum in the chamber and heat is directed at the item to raise the temperature of the item to less than 160° F., particularly between 120° F. to 150° F. Apparatus can dry veneer in less than five minutes.

    摘要翻译： 提供了一种装置和方法，用于通过物品中的水分蒸发来干燥胶合板或其它物品。 设备具有带框架的绝缘室和带门的抽屉。 抽屉的网眼表面支撑用于在室内的低于大气压的加热器干燥的物品。 将物品放置在设备的抽屉的网格层上，并用诸如另一层网的紧固件固定。 带有紧固件的抽屉放置在设备的室内。 当抽屉完全接合在室内时，干燥装置用气密密封封闭。 泵在室内抽真空，热量指向物品，以将物品的温度升高至小于160°F，特别是120°F至150°F。设备可在不到五分钟内干燥单板 。