公开(公告)号：US08552469B2

公开(公告)日：2013-10-08

申请号：US11862585

申请日：2007-09-27

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC分类号： H01L29/66 ,  H01L29/47

CPC分类号： H01L27/0788 ,  H01L27/0255 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/47 ,  H01L29/866 ,  H01L29/872

摘要： There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third anode diffusion layer formed in the epitaxial layer so as to surround the first and second anode diffusion layers and to extend toward the cathode diffusion layers, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.

摘要翻译： 在肖特基势垒二极管中存在反向漏电流变得过大的问题。 本发明的半导体器件包括形成在N型外延层中的P型第一和第二阳极扩散层，在外延层中形成的N型阴极扩散层，形成在外延层中的P型第三阳极扩散层 以便围绕第一和第二阳极扩散层并朝向阴极扩散层延伸，以及形成在第一和第二阳极扩散层上的肖特基势垒金属层。

公开(公告)号：US07999333B2

公开(公告)日：2011-08-16

申请号：US11391166

申请日：2006-03-27

申请人： Shuichi Kikuch ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuch ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of the present invention, an epitaxial layer is deposited on a substrate, and an LDMOSFET is formed in one region divided by an isolation region. In a region where a wiring layer connected to a drain electrode traverses a top surface of the isolation region, a conductive plate having a ground electric potential and another conductive plate in a floating state are formed under the wiring layer. With this structure, electric field is reduced in the vicinity of the isolation region under the wiring layer, whereby a withstand voltage of the LDMOSFET is increased.

摘要翻译： 在现有的半导体装置中，存在如下问题：在施加高电位的布线层横越隔离区域的上表面的区域中，耐电压劣化。 在本发明的半导体器件中，在衬底上沉积外延层，并且在由隔离区域划分的一个区域中形成LDMOSFET。 在与漏电极连接的布线层穿过隔离区域的上表面的区域中，在布线层的下方形成具有接地电位的导电板和浮置状态的另一导电板。 利用这种结构，在布线层下面的隔离区附近减小了电场，从而提高了LDMOSFET的耐受电压。

公开(公告)号：US07652307B2

公开(公告)日：2010-01-26

申请号：US11516733

申请日：2006-09-07

申请人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

发明人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

IPC分类号： H01L29/00

CPC分类号： H01L29/0696 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/7816

摘要： In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

摘要翻译： 在本发明的半导体器件中，MOS晶体管被设置为椭圆形。 分别使用椭圆形状的线性区域作为有效区域，椭圆形状的圆形区域分别用作非活性区域。 在每个非活性区域中，形成P型扩散层以与圆形重合。 另一个P型扩散层形成在一个非活性区域的一部分中。 这些P型扩散层形成为浮动扩散层，电容耦合到绝缘层上的金属层，并且呈现分别施加预定电位的状态。 这种结构使得有可能保持有源区的电流性能，同时提高无源区的耐压特性。

公开(公告)号：US20060220166A1

公开(公告)日：2006-10-05

申请号：US11395599

申请日：2006-03-30

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L29/861

CPC分类号： H01L29/872 ,  H01L29/866

摘要： In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

摘要翻译： 在本发明的半导体器件中，在形成在基板上的外延层上形成用于保护器件的保护二极管。 在外延层的表面上形成肖特基势垒金属层，在肖特基势垒金属层的端部的下部形成P型扩散层。 然后，形成P型扩散层以连接到P型扩散层并延伸到阴极区。 在P型扩散层的上方形成有施加了阳极电极的金属层，能够得到场板效应。 这种结构减小了耗尽层的曲率的大的变化，从而提高了保护二极管的耐电压特性。

公开(公告)号：US07737523B2

公开(公告)日：2010-06-15

申请号：US11395599

申请日：2006-03-30

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L29/93

CPC分类号： H01L29/872 ,  H01L29/866

摘要： In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

摘要翻译： 在本发明的半导体器件中，在形成在基板上的外延层上形成用于保护器件的保护二极管。 在外延层的表面上形成肖特基势垒金属层，在肖特基势垒金属层的端部的下部形成P型扩散层。 然后，形成P型扩散层以连接到P型扩散层并延伸到阴极区。 在P型扩散层的上方形成有施加了阳极电极的金属层，能够得到场板效应。 这种结构减小了耗尽层的曲率的大的变化，从而提高了保护二极管的耐电压特性。

公开(公告)号：US20060244091A1

公开(公告)日：2006-11-02

申请号：US11395890

申请日：2006-03-30

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L31/07

CPC分类号： H01L29/872 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/8611 ,  H01L29/868

摘要： In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, P-type diffusion layers are formed in a floating state closer to a cathode region side than the P-type diffusion layer, and are capacitively coupled with a metal layer to which an anode potential is applied. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

摘要翻译： 在本发明的半导体器件中，在形成在基板上的外延层上形成用于保护器件的保护二极管。 在外延层的表面上形成肖特基势垒金属层，在肖特基势垒金属层的端部的下部形成P型扩散层。 然后，P型扩散层形成为比P型扩散层更靠近阴极区域的浮置状态，并且与施加有阳极电位的金属层电容耦合。 这种结构减小了耗尽层的曲率的大的变化，从而提高了保护二极管的耐电压特性。

公开(公告)号：US07067899B2

公开(公告)日：2006-06-27

申请号：US10950610

申请日：2004-09-27

申请人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

发明人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC分类号： H01L29/00

CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L27/0821

摘要： A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

摘要翻译： 根据本发明的半导体集成电路器件包括在用作小信号部分的岛区中的衬底和第一外延层之间的N型嵌入扩散区域。 因此，衬底和第一外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

公开(公告)号：US06566728B1

公开(公告)日：2003-05-20

申请号：US09678555

申请日：2000-10-04

申请人： Shigeaki Okawa ,  Toshiyuki Ohkoda ,  Yoshiaki Ohbayashi ,  Mamoru Yasuda ,  Shinichi Saeki ,  Shuji Osawa

发明人： Shigeaki Okawa ,  Toshiyuki Ohkoda ,  Yoshiaki Ohbayashi ,  Mamoru Yasuda ,  Shinichi Saeki ,  Shuji Osawa

IPC分类号： H01L2900

CPC分类号： H04R19/005 ,  H04R19/04

摘要： First, a stationary electrode layer is formed over a semiconductor substrate and an integrated network is composed in a circuit element area around the stationary electrode layer by electrode wiring forming each circuit element. A spacer is arranged on a passivation film in plural places. A dummy island is formed in an area between the circuit element area and the stationary electrode layer area. Supply potential Vcc is applied to the dummy island and ground potential GND is applied to a P+-type separated area.

摘要翻译： 首先，在半导体衬底上形成固定电极层，并且通过形成每个电路元件的电极布线，在固定电极层周围的电路元件区域中形成集成网络。 在多个位置上在隔离膜上设置间隔物。 在电路元件区域和固定电极层区域之间的区域中形成虚设的岛。 将供电电位Vcc施加到虚拟岛，将接地电位GND施加到P +型分离区域。

公开(公告)号：US06545337B2

公开(公告)日：2003-04-08

申请号：US09946216

申请日：2001-09-05

申请人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

发明人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

IPC分类号： H01L2900

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76297 ,  H01L21/8228 ,  H01L27/1203

摘要： Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxial layers and substrate are etched in a V-groove. Each etched region is dielectrically isolated by the poly-Si (42).

摘要翻译： 当形成集电极区域（32,33）时，通过层叠4个外延层，能够承受高电压的膜的集电极区域（32,33）。 为了减少由晶体管（21,22）之间的干扰引起的影响并且还减少了寄生晶体管，外延层和衬底被蚀刻在V沟槽中。 每个蚀刻区域被多晶硅（42）介电隔离。

公开(公告)号：US06528379B2

公开(公告)日：2003-03-04

申请号：US09946948

申请日：2001-09-05

申请人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

发明人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

IPC分类号： H01L29788

CPC分类号： H01L21/76297 ,  H01L21/76264 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1203

摘要： A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each buried layer is diffused to connect, and etched in V-groove. By that, the collector region and collector taking-out region made thick in film are formed at the same time so as to realize the semiconductor integrated circuit device of high withstanding voltage.