公开(公告)号：US09379230B2

公开(公告)日：2016-06-28

申请号：US13554117

申请日：2012-07-20

申请人： Shuichi Tomabechi

发明人： Shuichi Tomabechi

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L29/423

CPC分类号： H01L29/7787 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0259 ,  H01L21/02667 ,  H01L29/2003 ,  H01L29/4236

摘要： A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is in an amorphous state in a peripheral area at an outer peripheral part of the substrate, and the protection layer is crystallized in an internal area of the protection layer that is inside the peripheral area of the protection layer.

摘要翻译： 半导体晶体基板包括基板; 以及通过在衬底的表面上施加氮化物而形成的保护层。 保护层在基板的外周部的周边区域处于非晶状态，保护层在保护层的保护层的周边区域内部的内部区域中结晶化。

公开(公告)号：US20130069072A1

公开(公告)日：2013-03-21

申请号：US13554117

申请日：2012-07-20

申请人： Shuichi TOMABECHI

发明人： Shuichi TOMABECHI

IPC分类号： H01L21/20 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0259 ,  H01L21/02667 ,  H01L29/2003 ,  H01L29/4236

摘要： A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is in an amorphous state in a peripheral area at an outer peripheral part of the substrate, and the protection layer is crystallized in an internal area of the protection layer that is inside the peripheral area of the protection layer.

摘要翻译： 半导体晶体基板包括基板; 以及通过在衬底的表面上施加氮化物而形成的保护层。 保护层在基板的外周部的周边区域处于非晶状态，保护层在保护层的保护层的周边区域内部的内部区域中结晶化。

公开(公告)号：US08962409B2

公开(公告)日：2015-02-24

申请号：US13569536

申请日：2012-08-08

申请人： Shuichi Tomabechi

发明人： Shuichi Tomabechi

IPC分类号： H01L21/337 ,  H01L29/778 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/66462

摘要： A method for fabricating a semiconductor device is disclosed. The method includes sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate, forming a dielectric layer having an opening after the forming of the semiconductor cap layer, forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer, and forming a gate electrode on the third semiconductor layer.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括在基板上依次形成第一半导体层，第二半导体层和含有p型杂质元素的半导体盖层，形成在形成半导体盖层之后具有开口的电介质层，形成第三半导体 在从电介质层的开口露出的半导体盖层上含有p型杂质元素的层，在第三半导体层上形成栅电极。

公开(公告)号：US08592823B2

公开(公告)日：2013-11-26

申请号：US13548324

申请日：2012-07-13

申请人： Junji Kotani ,  Tetsuro Ishiguro ,  Shuichi Tomabechi

发明人： Junji Kotani ,  Tetsuro Ishiguro ,  Shuichi Tomabechi

IPC分类号： H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/66462

摘要： A compound semiconductor device includes: a substrate; a GaN compound semiconductor multilayer structure disposed over the substrate; and a stress relief layer which is AlN-based and which is disposed between the substrate and the GaN compound semiconductor multilayer structure, wherein a surface of the stress relief layer that is in contact with the GaN compound semiconductor multilayer structure includes recesses that have a depth of 5 nm or more and that are formed at a number density of 2×1010 cm−2 or more.

摘要翻译： 一种化合物半导体器件，包括：衬底; 设置在所述基板上的GaN化合物半导体多层结构; 以及设置在所述基板与所述GaN化合物半导体多层结构体之间的基于AlN的应力消除层，其中与所述GaN化合物半导体多层结构接触的所述应力消除层的表面包括具有深度 5nm以上，并且以2×10 10 cm -2以上的数密度形成。

公开(公告)号：US20130043489A1

公开(公告)日：2013-02-21

申请号：US13548324

申请日：2012-07-13

申请人： Junji Kotani ,  Tetsuro Ishiguro ,  Shuichi Tomabechi

发明人： Junji Kotani ,  Tetsuro Ishiguro ,  Shuichi Tomabechi

IPC分类号： H01L29/20 ,  H01L29/161

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/66462

摘要： A compound semiconductor device includes: a substrate; a GaN compound semiconductor multilayer structure disposed over the substrate; and a stress relief layer which is AlN-based and which is disposed between the substrate and the GaN compound semiconductor multilayer structure, wherein a surface of the stress relief layer that is in contact with the GaN compound semiconductor multilayer structure includes recesses that have a depth of 5 nm or more and that are formed at a number density of 2×1010 cm−2 or more.

摘要翻译： 一种化合物半导体器件，包括：衬底; 设置在所述基板上的GaN化合物半导体多层结构; 以及设置在所述基板与所述GaN化合物半导体多层结构体之间的基于AlN的应力消除层，其中与所述GaN化合物半导体多层结构接触的所述应力消除层的表面包括具有深度 5nm以上，并且以2×10 10 cm -2以上的数密度形成。

公开(公告)号：US20130010824A1

公开(公告)日：2013-01-10

申请号：US13611099

申请日：2012-09-12

申请人： Shigekazu OKUMURA ,  Mitsuru Ekawa ,  Shuichi Tomabechi ,  Ayahito Uetake

发明人： Shigekazu OKUMURA ,  Mitsuru Ekawa ,  Shuichi Tomabechi ,  Ayahito Uetake

IPC分类号： H01S5/02 ,  H01L33/02

CPC分类号： H01S5/2081 ,  B82Y20/00 ,  H01S5/02288 ,  H01S5/026 ,  H01S5/0265 ,  H01S5/12 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/3211 ,  H01S5/34306

摘要： A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle θ greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.

摘要翻译： 半导体光学集成器件包括形成在衬底的（001）平面上的第一半导体光学器件和第二半导体光学器件，所述第二半导体光学器件形成在从第一半导体光学器件（110）取向的衬底的（001）面上 并且其光学连接到第一半导体光学器件。 第一半导体光学器件包括第一芯层和形成在第一芯层上并且在形成角度的第二半导体光学器件侧的侧面上的晶体表面的第一覆盖层; 大于或等于55度且小于或等于90度与（001）面。

公开(公告)号：US08565279B2

公开(公告)日：2013-10-22

申请号：US13611099

申请日：2012-09-12

申请人： Shigekazu Okumura ,  Mitsuru Ekawa ,  Shuichi Tomabechi ,  Ayahito Uetake

发明人： Shigekazu Okumura ,  Mitsuru Ekawa ,  Shuichi Tomabechi ,  Ayahito Uetake

IPC分类号： H01S5/00

CPC分类号： H01S5/2081 ,  B82Y20/00 ,  H01S5/02288 ,  H01S5/026 ,  H01S5/0265 ,  H01S5/12 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/3211 ,  H01S5/34306

摘要： A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle θ greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.

摘要翻译： 半导体光学集成器件包括形成在衬底的（001）平面上的第一半导体光学器件和第二半导体光学器件，所述第二半导体光学器件形成在从第一半导体光学器件（110）取向的衬底的（001）面上 并且其光学连接到第一半导体光学器件。 第一半导体光学器件包括第一芯层和第一覆层，其形成在第一芯层上，并且在第二半导体光学器件侧上具有形成角度θ大于或等于55°的一侧的晶体表面 度和小于或等于90度与（001）面。

公开(公告)号：US20060145276A1

公开(公告)日：2006-07-06

申请号：US11111995

申请日：2005-04-22

申请人： Shuichi Tomabechi ,  Tsuyoshi Yamamoto

发明人： Shuichi Tomabechi ,  Tsuyoshi Yamamoto

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01S5/5009 ,  B82Y10/00 ,  B82Y20/00 ,  H01S5/2237 ,  H01S5/2272 ,  H01S5/2275 ,  H01S5/3412

摘要： An optical semiconductor device such as, for example, a quantum dot SOA and a fabrication method therefor are disclosed wherein an active layer and a current constriction structure can be formed leftwardly and rightwardly symmetrically to minimize the polarization dependency. The fabrication method for an optical semiconductor device includes the steps of forming a semiconductor layer on a semiconductor substrate, forming a groove by removing the semiconductor layer at an opening of a mask, forming a first clad layer in the form of a projection having two symmetrical inclined faces in the groove by selective growth by using the mask as a selective growth mask, forming an active layer on the two inclined faces of the first clad layer, and removing the mask and burying the active layer with a second clad layer.

公开(公告)号：US20130330867A1

公开(公告)日：2013-12-12

申请号：US13966592

申请日：2013-08-14

申请人： Shigekazu OKUMURA ,  Mitsuru EKAWA ,  Shuichi TOMABECHI ,  Ayahito UETAKE

发明人： Shigekazu OKUMURA ,  Mitsuru EKAWA ,  Shuichi TOMABECHI ,  Ayahito UETAKE

IPC分类号： H01S5/20

CPC分类号： H01S5/2081 ,  B82Y20/00 ,  H01S5/02288 ,  H01S5/026 ,  H01S5/0265 ,  H01S5/12 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/3211 ,  H01S5/34306

摘要： A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle θ greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.

摘要翻译： 半导体光学集成器件包括形成在衬底的（001）平面上的第一半导体光学器件和第二半导体光学器件，所述第二半导体光学器件形成在从第一半导体光学器件（110）取向的衬底的（001）面上 并且其光学连接到第一半导体光学器件。 第一半导体光学器件包括第一芯层和第一覆层，其形成在第一芯层上，并且在第二半导体光学器件侧上具有形成角度θ大于或等于55°的一侧的晶体表面 度和小于或等于90度与（001）面。

公开(公告)号：US20130075788A1

公开(公告)日：2013-03-28

申请号：US13569536

申请日：2012-08-08

申请人： Shuichi TOMABECHI

发明人： Shuichi TOMABECHI

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L21/335

CPC分类号： H01L29/7787 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/66462

摘要： A method for fabricating a semiconductor device is disclosed. The method includes sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate, forming a dielectric layer having an opening after the forming of the semiconductor cap layer, forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer, and forming a gate electrode on the third semiconductor layer.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括在基板上依次形成第一半导体层，第二半导体层和含有p型杂质元素的半导体盖层，形成在形成半导体盖层之后具有开口的电介质层，形成第三半导体 在从电介质层的开口露出的半导体盖层上含有p型杂质元素的层，在第三半导体层上形成栅电极。