公开(公告)号：US4583282A

公开(公告)日：1986-04-22

申请号：US650969

申请日：1984-09-14

申请人： Terry S. Hulseweh ,  Carroll Casteel

发明人： Terry S. Hulseweh ,  Carroll Casteel

IPC分类号： H01L21/033 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/80 ,  H01L21/76

CPC分类号： H01L21/763 ,  H01L21/033 ,  H01L21/74 ,  H01L21/76216 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/125 ,  Y10S148/128 ,  Y10S438/969

摘要： A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

摘要翻译： 描述了用于在公共衬底中制造隔离半导体器件的工艺，其具有自对准和预定位的隔离壁，掩埋层和通道停止。 隔离壁由介质区域和多晶半导体区域的堆叠布置形成，该区域用作场防护体的掺杂通道阻挡区域上方。 单个掩模层确定隔离壁，通道停止物和掩埋层的掩埋部分的位置和间隔。

公开(公告)号：US4614021A

公开(公告)日：1986-09-30

申请号：US717343

申请日：1985-03-29

申请人： Terry S. Hulseweh

发明人： Terry S. Hulseweh

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/312

CPC分类号： H01L21/76885 ,  H01L21/76819

摘要： An improved means and method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits. A lower first conductor layer is formed on the device substrate and covered with an electrically conducting etch-stop layer and a second conductor layer. The second conductor layer is masked to define the conductive via and etched selectively and anisotropically until the etch-stop layer is reached. The exposed portions of the etch-stop layer are then removed. The remaining portions of the etch-stop layer and second conductor layer together form the conductive pillar. The lower first metal layer is patterned and then covered with a planarizing layer, such as a polyimide, having a thickness at least equal to the height of the pillar. The planarizing layer is uniformly etched to expose the top of the pillar and then an upper metal layer deposited over the remaining polyimide and in contact with the top of the pillar. The remaining polyimide acts as the interlayer dielectric.

摘要翻译： 描述了一种改进的装置和方法，用于在诸如集成电路的平面电子结构上的多层导体之间的通孔中提供导电柱。 下部第一导体层形成在器件衬底上并覆盖有导电蚀刻停止层和第二导体层。 第二导体层被掩蔽以限定导电通孔并且被选择性地和各向异性地蚀刻，直到达到蚀刻停止层。 然后去除蚀刻停止层的暴露部分。 蚀刻停止层和第二导体层的其余部分一起形成导电柱。 下部第一金属层被图案化，然后被平坦化层（例如聚酰亚胺）覆盖，其厚度至少等于柱的高度。 均匀蚀刻平坦化层以暴露柱的顶部，然后沉积在剩余聚酰亚胺上并与柱的顶部接触的上金属层。 剩余的聚酰亚胺作为层间电介质。

公开(公告)号：US4573257A

公开(公告)日：1986-03-04

申请号：US650931

申请日：1984-09-14

申请人： Terry S. Hulseweh

发明人： Terry S. Hulseweh

IPC分类号： H01L21/033 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/74 ,  H01L21/762 ,  H01L21/20 ,  H01L21/76

CPC分类号： H01L21/32134 ,  H01L21/033 ,  H01L21/32155 ,  H01L21/74 ,  H01L21/76216 ,  Y10S148/085 ,  Y10S148/102 ,  Y10S148/106 ,  Y10S148/111 ,  Y10S148/122

摘要： A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e.g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

摘要翻译： 描述了用于在半导体器件和集成电路中制造自对准掩埋掺杂区域的过程，其避免了对器件的有源部分中的掩埋掺杂区域的描绘的任何需要。 避免描绘改善了用于覆盖掩埋掺杂区域的外延层的质量，从而提高了整体性能和产量。 结合单个掩模图案使用多个掩模层以实现自对准。 一个掩模层由具有可修改蚀刻速率的材料组成。 多晶硅 单晶衬底的一部分被制成非单晶，并用作对准键，该对准键通过在无线衬底掩埋掺杂区域上生长的外延层传播。 可以精确地控制自对准掩埋掺杂区域的尺寸和分离。

公开(公告)号：US4423548A

公开(公告)日：1984-01-03

申请号：US280190

申请日：1981-07-06

申请人： Terry S. Hulseweh

发明人： Terry S. Hulseweh

IPC分类号： G11C5/00 ,  H01L21/56

CPC分类号： G11C5/005 ,  Y10S438/953

摘要： A structure is provided which affords radiation protection to semiconductor devices and which specifically prevents soft failures in semiconductor memories caused by alpha particle radiation. The protection is provided by a metallic radiation shield formed on but insulated from the semiconductor memory array. The radiation shield is formed on the semiconductor devices while they are still in wafer form but after the normal device fabrication has been completed.

摘要翻译： 提供了提供对半导体器件的辐射保护并且具体地防止由α粒子辐射引起的半导体存储器中的软故障的结构。 保护由在半导体存储器阵列上形成绝缘的金属辐射屏蔽提供。 在半导体器件仍然是晶片形式但是在正常的器件制造完成之后，形成辐射屏蔽。

公开(公告)号：US4574469A

公开(公告)日：1986-03-11

申请号：US650964

申请日：1984-09-14

申请人： Sal Mastroianni ,  Carroll Casteel ,  Terry S. Hulseweh

发明人： Sal Mastroianni ,  Carroll Casteel ,  Terry S. Hulseweh

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/223 ,  H01L21/31 ,  H01L21/74

CPC分类号： H01L21/76216 ,  Y10S148/035 ,  Y10S148/083 ,  Y10S148/086 ,  Y10S148/117 ,  Y10S148/122 ,  Y10S438/969

摘要： A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.

摘要翻译： 描述了用于在公共衬底中制造隔离半导体器件的工艺，其具有自对准和预定位的隔离壁，掩埋层和通道停止。 隔离壁由掺杂的通道阻挡区域上方的电介质区域和非单晶半导体区域的堆叠布置形成。 单个掩模层确定隔离壁的非单晶部分，通道停止部和掩埋层的位置和间隔。