公开(公告)号：US4486944A

公开(公告)日：1984-12-11

申请号：US485732

申请日：1983-04-18

申请人： Kim C. Hardee

发明人： Kim C. Hardee

IPC分类号： G11C11/412 ,  H01L23/522 ,  H01L27/06 ,  H01L27/11 ,  H01L21/80

CPC分类号： H01L27/0688 ,  G11C11/412 ,  H01L23/522 ,  H01L27/1112 ,  H01L2924/0002

摘要： A single polycrystalline silicon configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.

摘要翻译： 描述了用于静态MOS RAM中的存储单元的单个多晶硅结构及其制造方法。 利用三个导电区域形成每个存储单元。 在衬底中形成第一导电区域以产生掩埋地线和晶体管的源极和漏极。 第二导电区域形成在绝缘层内并在第一导电区域之上，以产生字线，晶体管的栅极区域，负载电阻器和电源线。 电源线直接位于地线上方并平行。 在绝缘层的表面上形成第三导电区域以产生数据线。 通过该配置减少了处理步骤的数量和存储器单元的大小。

公开(公告)号：US4525924A

公开(公告)日：1985-07-02

申请号：US503078

申请日：1983-06-13

申请人： Horst Schafer

发明人： Horst Schafer

IPC分类号： H01L21/304 ,  H01L21/78 ,  H01L25/07 ,  H01L27/08 ,  H01L29/86 ,  H01L21/461 ,  H01L21/80

CPC分类号： H01L21/304 ,  H01L21/78 ,  H01L25/072 ,  H01L27/0814 ,  H01L2924/0002 ,  H01L2924/10157 ,  H01L2924/10158

摘要： A method for producing a semiconductor arrangement of two antiparallel connected diodes comprising a semiconductor body which includes a base region of one conductivity type and a zone adjacent each side of the base region. Each zone forms a pn-junction with the base region and thus a diode structure and is offset with respect to the other zone. The major surfaces formed by each base region and one of the two zones are provided with a contact metal coating so as to electrically connect the two diode structures. In accordance with this method, a layer sequence of three zones with pn-junctions therebetween is formed by diffusion on a semiconductor starting disc. Then, mutually parallel recesses are produced with the aid of masking in each major surface of the disc according to a strip-shaped structure, offset with respect to that of the other major surface, by removing material to beyond the respective pn-junction. Both major surfaces are metallized and the disc is divided along the recesses into semiconductor arrangements.

摘要翻译： PCT No.PCT / DE79 / 00145 Sec。 371日期1980年8月14日 102（e）日期1980年8月14日PCT提交1979年12月11日PCT公布。 第WO80 / 01334号公报 日期：1980年6月26日。一种用于制造两个反并联连接二极管的半导体装置的方法，包括半导体本体，其包括一个导电类型的基极区域和与该基极区域的每一侧相邻的区域。 每个区域与基极区域形成pn结，从而形成二极管结构并相对于另一个区域偏移。 由每个基底区域和两个区域之一形成的主表面设置有接触金属涂层，以便电连接两个二极管结构。 根据该方法，通过在半导体启动盘上的扩散形成其间具有pn结的三个区域的层序列。 然后，借助于通过将材料移除到相应的pn结以外的方式，通过根据条形结构掩模在盘的每个主表面中相对于另一个主表面偏移而产生相互平行的凹陷。 两个主表面被金属化，并且盘沿着凹槽被分割为半导体布置。

公开(公告)号：US4633572A

公开(公告)日：1987-01-06

申请号：US790382

申请日：1985-10-23

申请人： Randy A. Rusch ,  Douglas A. Kittle ,  Bernhard G. Ulfers ,  Stephen L. Inman

发明人： Randy A. Rusch ,  Douglas A. Kittle ,  Bernhard G. Ulfers ,  Stephen L. Inman

IPC分类号： H01L27/02 ,  H01L21/263 ,  H01L21/80

CPC分类号： H01L27/0214

摘要： An enhancement implant used in late programming of a ROM in an integrated circuit is combined with a depletion implant used much earlier in the fabrication process to also permit late programming of power paths in the integrated circuit. The implants must be matched and the IC heated after the enhancement implant.

摘要翻译： 用于集成电路中的ROM的后期编程中的增强注入与在制造过程中早得多使用的耗尽种植体组合，还允许集成电路中的电源路径的后期编程。 植入物必须匹配，并且IC在加强植入物后被加热。

公开(公告)号：US4583282A

公开(公告)日：1986-04-22

申请号：US650969

申请日：1984-09-14

申请人： Terry S. Hulseweh ,  Carroll Casteel

发明人： Terry S. Hulseweh ,  Carroll Casteel

IPC分类号： H01L21/033 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/80 ,  H01L21/76

CPC分类号： H01L21/763 ,  H01L21/033 ,  H01L21/74 ,  H01L21/76216 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/125 ,  Y10S148/128 ,  Y10S438/969

摘要： A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

摘要翻译： 描述了用于在公共衬底中制造隔离半导体器件的工艺，其具有自对准和预定位的隔离壁，掩埋层和通道停止。 隔离壁由介质区域和多晶半导体区域的堆叠布置形成，该区域用作场防护体的掺杂通道阻挡区域上方。 单个掩模层确定隔离壁，通道停止物和掩埋层的掩埋部分的位置和间隔。

公开(公告)号：US4475280A

公开(公告)日：1984-10-09

申请号：US450687

申请日：1982-12-17

申请人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

发明人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

IPC分类号： H01L27/02 ,  H01L27/082 ,  H03K17/28 ,  H03K17/60 ,  H03K17/795 ,  H01L21/80

CPC分类号： H01L27/0244 ,  H01L27/0821 ,  H01L27/0825 ,  H03K17/28 ,  H03K17/60 ,  H03K17/795

摘要： An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.

摘要翻译： 公开了一种包含由低电压半导体器件控制的高电压半导体器件的集成电路，包括其制造方法。 与用于制造离散高压功率晶体管的工艺相比，能够在同一芯片上实现复杂逻辑功能的低电压器件在制造过程中只需一个简单的额外步骤。 植入低电压器件的加工过程不会显着降低与分立功率晶体管相关的原始能力。 描述了侧向显影和垂直显影的装置。 集成电路将I2L逻辑与功率达林顿晶体管相结合。 大面积离子注入允许在一个衬底上制造低压和高压器件。 所得到的集成电路允许通过简单或复杂的控制功能来控制多个负载。

公开(公告)号：US5366922A

公开(公告)日：1994-11-22

申请号：US155341

申请日：1993-11-22

申请人： Kenji Aoki ,  Naoto Saito

发明人： Kenji Aoki ,  Naoto Saito

IPC分类号： H01L21/225 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/80

CPC分类号： H01L21/823814 ,  H01L21/2254 ,  H01L27/0928 ,  Y10S148/034

摘要： The method of producing a CMOS transistor device. A pair of device regions are formed in separated relation from each other by a field oxide film on a pair of corresponding well regions formed in a semiconductor substrate. A gate insulating film and a gate electrode is sequentially formed on each of the device regions. The gate insulating film is removed through a mask of the patterned gate electrode to expose a silicon active surface at least in one of the device regions. A diborane gas containing P type impurity of boron is applied to the silicon active surface to form thereon a boron absorption film. N type impurity of arsenic is doped into the other device region by ion implantation to form N type of source and drain regions while masking the one device region. The boron is diffused from the adsorption film into the one device region to form P type of source and drain regions by annealing of the substrate.

摘要翻译： 制造CMOS晶体管器件的方法。 一对器件区域通过形成在半导体衬底中的一对对应阱区域上的场氧化膜彼此分开地形成。 栅极绝缘膜和栅电极依次形成在每个器件区域上。 通过图案化栅电极的掩模去除栅极绝缘膜，以在至少一个器件区域中露出硅有源表面。 将含有P型杂质硼的乙硼烷气体施加到硅活性表面上以在其上形成硼吸收膜。 通过离子注入将N型杂质砷掺杂到另一个器件区域中，以形成N型源极和漏极区域，同时掩蔽一个器件区域。 硼从吸附膜扩散到一个器件区域中，通过衬底退火形成P型源极和漏极区。

公开(公告)号：US4700460A

公开(公告)日：1987-10-20

申请号：US924865

申请日：1986-10-30

申请人： Gary M. Dolny ,  Lawrence A. Goodman

发明人： Gary M. Dolny ,  Lawrence A. Goodman

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/74 ,  H01L21/78 ,  H01L21/80

CPC分类号： H01L29/7813 ,  H01L29/66666 ,  H01L29/4236 ,  Y10S148/126

摘要： A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped. The silicon that is between the insulated gate and each wafer surface includes a relatively lightly doped voltage-supporting region contiguous with the insulated gate and the laterally adjacent silicon and a relatively heavily doped region between this voltage-supporting region and the surface. Additionally, the interface between the insulated gate and the laterally adjacent silicon has a low density of interface states.

摘要翻译： 具有相对主表面的硅晶片中的垂直MOSFET包括一个表面上的源电极，第二表面上的漏极电极和内部设置的绝缘栅极。 绝缘栅极和每个主表面之间的硅是第一导电类型，并且与绝缘栅极横向相邻的硅是第二导电类型，使得绝缘栅上的预定电压产生延伸预定的 距离进入横向相邻的硅。 形成反向沟道的横向相邻硅的部分是相对轻掺杂的材料，而横向相邻的硅的其它区域是相对重掺杂的。 在绝缘栅极和每个晶片表面之间的硅包括与绝缘栅极和横向相邻的硅连接的相对轻掺杂的电压支撑区域和在该电压支撑区域和表面之间的相对重掺杂的区域。 此外，绝缘栅极和横向相邻硅之间的界面具有低密度的界面态。

公开(公告)号：US4586240A

公开(公告)日：1986-05-06

申请号：US748940

申请日：1985-06-26

申请人： Scott C. Blackstone ,  Lubomir L. Jastrzebski ,  John F. Corboy, Jr.

发明人： Scott C. Blackstone ,  Lubomir L. Jastrzebski ,  John F. Corboy, Jr.

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/74 ,  H01L21/78 ,  H01L21/80 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/4236 ,  Y10S148/019 ,  Y10S148/123 ,  Y10S148/126

摘要： A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.

摘要翻译： 公开了一种垂直IGFET，其包括在一个主表面上具有源电极的基本上平面的硅晶片，并且在相对的主表面上具有漏电极。 绝缘栅极包括由绝缘层包围的导电指状部分，内部设置在硅晶片中，使得施加到栅电极的预定电压将调节源极和漏极之间的电流。 该器件利用外延横向过生长技术制造，用于在设置在硅衬底上的绝缘栅极上沉积单晶硅。

公开(公告)号：US5394337A

公开(公告)日：1995-02-28

申请号：US967671

申请日：1992-10-23

申请人： Keisuke Shinjo

发明人： Keisuke Shinjo

IPC分类号： H01L21/82 ,  G06F17/50 ,  G06F15/60 ,  H01L21/80

CPC分类号： G06F17/5077

摘要： A method and apparatus for wire routing of a semiconductor integrated circuit wherein the interconnection between the functional blocks disposed on a chip of the semiconductor integrated circuit having four or more wiring layers is implemented by computers. A plurality of adjacent wiring layers form a single set, and for at least two sets, the wire routing between terminals of the functional blocks lying on the wiring layers formed by the sets is carried out for each set independently from the other set. A plurality of computers are used, which communicate with each other through their network. A file system of one computer is shared between the two computers so that the wire routing process program, input information on the wire routing and a wire routing result can be stored within the shared file system, whereby an efficient concurrent processing is possible and the processing speed can be improved while the number of wiring layers dealt with by each wire routing process are reduced.

摘要翻译： 一种用于半导体集成电路的布线方法和装置，其中设置在具有四个或更多布线层的半导体集成电路的芯片上的功能块之间的互连由计算机实现。 多个相邻布线层形成一组，并且对于至少两组，位于由该组形成的布线层上的功能块的端子之间的布线在每个组中独立于另一组进行。 使用多个通过其网络相互通信的计算机。 一台计算机的文件系统在两台计算机之间共享，使得线路路由处理程序，有线路由输入信息和有线路由结果可以存储在共享文件系统内，从而可以进行有效的并发处理， 可以提高速度，同时通过每个线路布线处理处理的配线层的数量减少。

公开(公告)号：US5300461A

公开(公告)日：1994-04-05

申请号：US8469

申请日：1993-01-25

申请人： Chiu H. Ting

发明人： Chiu H. Ting

IPC分类号： G11C16/18 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/80

CPC分类号： H01L23/564 ,  G11C16/18 ,  H01L23/291 ,  H01L23/3171 ,  H01L2924/0002

摘要： Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

摘要翻译： 描述了形成密封芯片的结构和工艺。 这种密封芯片将大大简化封装要求，最终导致实现“无封装芯片”。 气密密封由两部分组成，其沉积在整个芯片顶部和侧表面上的极薄的钝化层和沉积在焊盘表面上的钝化层。 优选地，SiN作为芯片表面钝化层沉积，并且Ni被选择性地沉积为金属钝化层。 极薄的氮化物层将使SiN膜中的应力和氢的量最小化，并使由应力和氢引起的对器件性能的有害影响最小化。 金属钝化层的厚度可以与电介质层的厚度相同，以便得到平坦的表面，或者可以足够厚以便产生突出的金属钝化凸块。