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    Semiconductor memory device requiring refresh operation
    2.
    发明授权
    Semiconductor memory device requiring refresh operation 失效
    需要刷新操作的半导体存储器件

    公开(公告)号：US06813210B2

    公开(公告)日：2004-11-02

    申请号：US10300591

    申请日：2002-11-21

    申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

    发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

    IPC分类号： G11C700

    CPC分类号： G11C7/04 ,  G11C11/406

    摘要： The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

    摘要翻译： 半导体存储器件包括用于确定自刷新操作的刷新周期的刷新定时器。 刷新定时器包括电压调节器，环形振荡器和计数器。 电压调节器产生具有正温度特性的偏置电压。 环形振荡器根据偏置电压来改变脉冲信号的振荡周期。 计数器对规定数量的脉冲信号进行计数，并产生用于执行刷新操作的刷新信号。 因此，半导体存储器件根据温度变化而改变刷新周期，并且以适当的刷新周期执行刷新操作。

    Semiconductor memory device with complete inhibition of boosting of word line drive signal and method thereof
    4.
    发明授权
    Semiconductor memory device with complete inhibition of boosting of word line drive signal and method thereof 失效
    具有完全抑制字线驱动信号升压的半导体存储器件及其方法

    公开(公告)号：US5666313A

    公开(公告)日：1997-09-09

    申请号：US707364

    申请日：1996-09-04

    申请人： Tetsuichiro Ichiguchi

    发明人： Tetsuichiro Ichiguchi

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  G11C8/18 ,  G11C11/401 ,  G11C29/06 ,  G11C7/00

    CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C8/18

    摘要： A word line drive signal generating circuit, which generates a word line drive signal RX to a selected word line, includes an RX generating circuit responsive to an external row address strobe signal *RAS (or/RAS) for generating word line drive signal RX, a determination circuit responsive to an operating power supply voltage level or an externally applied signal for determining whether the word line drive signal RX should be boosted up, and a boosting circuit responsive to the word line drive signal RX and an output of determination circuit for boosting up the word line drive signal RX. The word line drive signal RX is boosted up to or above the operating power supply voltage level only when the determination circuit determines it to be necessary. Thereby, a high voltage is not normally applied to the word line, so that deterioration of breakdown voltage of the word line is prevented, and the reliability of the word line is improved.

    摘要翻译： 一个字线驱动信号产生电路，它产生一个字线驱动信号RX到选定的字线，它包括一个响应外部行地址选通信号* RAS（或/ RAS）的RX产生电路，用于产生字线驱动信号RX， 响应于工作电源电压电平的确定电路或用于确定字线驱动信号RX是否应被升压的外部施加的信号，以及响应于字线驱动信号RX的升压电路和用于升压的确定电路的输出 字线驱动信号RX。 只有当确定电路确定需要时，字线驱动信号RX被提升到等于或高于工作电源电压电平。 因此，通常不会对字线施加高电压，从而防止字线的击穿电压的劣化，并提高字线的可靠性。

    Semiconductor memory device having sense amplifier having improved activation timing thereof and operating method thereof
    6.
    发明授权
    Semiconductor memory device having sense amplifier having improved activation timing thereof and operating method thereof 失效
    具有读出放大器的半导体存储器件具有改进的激活时间及其操作方法

    公开(公告)号：US4916671A

    公开(公告)日：1990-04-10

    申请号：US313680

    申请日：1989-02-22

    申请人： Tetsuichiro Ichiguchi

    发明人： Tetsuichiro Ichiguchi

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401

    CPC分类号： G11C7/065

    摘要： A dynamic random access memory comprises memory cells (MA1-Man) and sense amplifies (SA1-SAn) in a memory array region III and memory cells (MB1-MBn) and sense amplifies (SB1-SBn) in a memory array region IV. In reading operation, first, the sense amplifiers in one region comprising a memory cell designated by an address signal are activated and then sense amplifiers in the other region are activated. As a result, since amplifying operation by the sense amplifiers is performed sequentially, a peak value of a current consumed by the amplification can be reduced.

    摘要翻译： 动态随机存取存储器包括存储器阵列区域III中的存储单元（MA1-Man）和读出放大器（SA1-SAn）和存储器单元（MB1-MBn），并读出存储器阵列区域IV中的SB1-SBn。 在读取操作中，首先，包括由地址信号指定的存储单元的一个区域中的读出放大器被激活，然后激活另一个区域中的读出放大器。 结果，由于依次执行读出放大器的放大操作，所以可以减小由放大消耗的电流的峰值。

    Semiconductor memory device switchable to twin memory cell configuration
    7.
    发明授权
    Semiconductor memory device switchable to twin memory cell configuration 失效
    半导体存储器件可切换到双存储单元配置

    公开(公告)号：US06775177B2

    公开(公告)日：2004-08-10

    申请号：US10298648

    申请日：2002-11-19

    申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

    发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

    IPC分类号： G11C1124

    CPC分类号： G11C11/405 ,  G11C7/1045 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4087

    摘要： A row address decoder of a semiconductor memory device generates internal row address signals RAD and /RAD by switching most significant bit and least significant bit of row address signals RA and /RA that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD and /RAD of the internal row address signals corresponding to the most significant bits RA and /RA of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

    摘要翻译： 通过切换行地址信号RA <0:11>和/ RA的最高有效位和最低有效位，半导体存储器件的行地址解码器产生内部行地址信号RAD <0:11>和/ RAD <0:11> 分别对应于地址信号A0至A11的<0:11>。 在双胞模式中，对应于不是行地址信号的最高有效位RA 11和/ RA 11的内部行地址信号的最低有效位RAD <0>和/ RAD <0> 使用的同时由行地址解码器选择，并且两个相邻的字线同时被激活。 因此，半导体存储器件中的存储单元的配置可以从正常的单个存储器单元类型切换到双存储单元类型。