利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.04 秒)

    Semiconductor memory device requiring refresh operation
    3.
    发明授权
    Semiconductor memory device requiring refresh operation 失效
    需要刷新操作的半导体存储器件

    公开(公告)号：US06813210B2

    公开(公告)日：2004-11-02

    申请号：US10300591

    申请日：2002-11-21

    申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

    发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

    IPC分类号： G11C700

    CPC分类号： G11C7/04 ,  G11C11/406

    摘要： The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

    摘要翻译： 半导体存储器件包括用于确定自刷新操作的刷新周期的刷新定时器。 刷新定时器包括电压调节器，环形振荡器和计数器。 电压调节器产生具有正温度特性的偏置电压。 环形振荡器根据偏置电压来改变脉冲信号的振荡周期。 计数器对规定数量的脉冲信号进行计数，并产生用于执行刷新操作的刷新信号。 因此，半导体存储器件根据温度变化而改变刷新周期，并且以适当的刷新周期执行刷新操作。

    Semiconductor memory device switchable to twin memory cell configuration
    5.
    发明授权
    Semiconductor memory device switchable to twin memory cell configuration 失效
    半导体存储器件可切换到双存储单元配置

    公开(公告)号：US06775177B2

    公开(公告)日：2004-08-10

    申请号：US10298648

    申请日：2002-11-19

    申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

    发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

    IPC分类号： G11C1124

    CPC分类号： G11C11/405 ,  G11C7/1045 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4087

    摘要： A row address decoder of a semiconductor memory device generates internal row address signals RAD and /RAD by switching most significant bit and least significant bit of row address signals RA and /RA that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD and /RAD of the internal row address signals corresponding to the most significant bits RA and /RA of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

    摘要翻译： 通过切换行地址信号RA <0:11>和/ RA的最高有效位和最低有效位，半导体存储器件的行地址解码器产生内部行地址信号RAD <0:11>和/ RAD <0:11> 分别对应于地址信号A0至A11的<0:11>。 在双胞模式中，对应于不是行地址信号的最高有效位RA 11和/ RA 11的内部行地址信号的最低有效位RAD <0>和/ RAD <0> 使用的同时由行地址解码器选择，并且两个相邻的字线同时被激活。 因此，半导体存储器件中的存储单元的配置可以从正常的单个存储器单元类型切换到双存储单元类型。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06717460B2

    公开(公告)日：2004-04-06

    申请号：US10211289

    申请日：2002-08-05

    申请人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto ,  Zengcheng Tian

    发明人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto ,  Zengcheng Tian

    IPC分类号： G05F110

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

    摘要： A level conversion circuit is provided, at an output, with an initialization circuit for setting the output signal of the level conversion circuit for generating a power cut enable signal controlling a deep power down mode to a predetermined inactive state upon power up. The initialization circuit is constituted by, for example, a capacitive element connected to the output node of the level conversion circuit to pull up the voltage of the output node upon power up, and a latch circuit latching the voltage level of the output node. When power is on, the power cut enable signal is forcibly inactivated by the initialization circuit to generate a periphery power supply voltage. The internal node of the level conversion circuit is initialized according to the output signal of a control circuit receiving the periphery power supply voltage as an operating power supply voltage. In semiconductor memory device having a deep power down mode, an internal voltage is generated reliably and properly upon power up of an internal voltage.

    摘要翻译： 在输出端提供电平转换电路，该初始化电路用于设置电平转换电路的输出信号，用于在上电时产生控制深度掉电模式至预定非活动状态的掉电使能信号。 初始化电路例如由与电平转换电路的输出节点连接的电容元件构成，以在上电时上拉输出节点的电压，以及锁存电路来锁存输出节点的电压电平。 当电源接通时，断电启动信号被初始化电路强制停用，以产生外围电源电压。 电平转换电路的内部节点根据接收外围电源电压的控制电路的输出信号作为工作电源电压进行初始化。 在具有深度掉电模式的半导体存储器件中，在内部电压上电时可靠且可靠地产生内部电压。

    Semiconductor device adaptable to a plurality of kinds of interfaces
    9.
    发明授权
    Semiconductor device adaptable to a plurality of kinds of interfaces 有权
    适用于多种界面的半导体装置

    公开(公告)号：US06784718B2

    公开(公告)日：2004-08-31

    申请号：US10231132

    申请日：2002-08-30

    申请人： Takeo Okamoto ,  Tadaaki Yamauchi ,  Shinichi Jinbo ,  Makoto Suwa ,  Junko Matsumoto

    发明人： Takeo Okamoto ,  Tadaaki Yamauchi ,  Shinichi Jinbo ,  Makoto Suwa ,  Junko Matsumoto

    IPC分类号： H03L500

    CPC分类号： G11C7/1087 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

    摘要： An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit. Even if the output power supply voltage varies to cause the input signal to change, whether the input signal is at H level or L level can accurately be determined and an internal signal is generated correctly

    摘要翻译： 输入电路包括：门电路，其接收决定输入信号的逻辑电平的输出电源电压或者接收输入信号的比较电路，以及取决于从不同于电源的焊盘提供的输出电源电压的基准电压 用于输出电路的焊盘。 即使输出电源电压变化，导致输入信号变化，输入信号是否处于H电平或L电平，可以准确地确定内部信号是否正确生成

    Semiconductor device
    10.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06744298B2

    公开(公告)日：2004-06-01

    申请号：US10209906

    申请日：2002-08-02

    申请人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto

    发明人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto

    IPC分类号： H03L500

    CPC分类号： G11C11/4072 ,  G11C7/20

    摘要： In the output circuit, at a subsequent stage of a gate circuit operating with a power supply voltage related to a first power supply voltage, a latch circuit formed of an inverter circuit and a MOS transistor is arranged, and is supplied with a second power supply voltage as an operating power supply voltage. An output buffer circuit is driven in accordance with an output signal of the latch circuit. When the first power supply voltage is powered down, the latch circuit receiving and operating with the second power supply voltage holds a signal voltage to be attained in a standby state and thus the output buffer circuit is reliably held in an output high impedance state. In a semiconductor device of a double power supply configuration, even when one power supply is powered down, the output buffer circuit can reliably be set to an output high impedance state.

    摘要翻译： 在输出电路中，在以与第一电源电压相关的电源电压工作的门电路的后续阶段，布置由逆变器电路和MOS晶体管形成的锁存电路，并且被提供有第二电源 电压作为工作电源电压。 根据锁存电路的输出信号驱动输出缓冲电路。 当第一电源电压断电时，以第二电源电压接收和操作的锁存电路在备用状态下保持要获得的信号电压，从而将输出缓冲电路可靠地保持在输出高阻抗状态。 在双电源配置的半导体器件中，即使当一个电源断电时，输出缓冲电路也可以可靠地设置为输出高阻抗状态。