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    Semiconductor device including field effect transistor with reduced electric field concentration
    2.
    发明授权
    Semiconductor device including field effect transistor with reduced electric field concentration 有权
    包括具有降低的电场浓度的场效应晶体管的半导体器件

    公开(公告)号：US08232609B2

    公开(公告)日：2012-07-31

    申请号：US12828328

    申请日：2010-07-01

    Applicant: Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    Inventor： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    IPC: H01L29/76

    CPC classification number: H01L29/4238 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/812

    Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

    Abstract translation: 半导体器件包括：半导体衬底; 在所述半导体衬底的顶表面处的杂质掺杂区域; 绝缘区域，位于半导体衬底的顶表面上的杂质掺杂区域周围; 杂质掺杂区上的栅电极; 位于所述杂质掺杂区域上的第一电极和第二电极，夹着所述栅电极; 位于所述绝缘区域上并连接到所述栅电极的第一焊盘; 在所述绝缘区域上跨越所述杂质掺杂区域面对所述第一焊盘的第二焊盘，并且连接到所述第二电极; 以及位于所述绝缘区域上的所述第一电极和所述第二焊盘之间的导体。

    Heterojunction field effect semiconductor device
    3.
    发明申请
    Heterojunction field effect semiconductor device 审中-公开
    异质结场效应半导体器件

    公开(公告)号：US20050263788A1

    公开(公告)日：2005-12-01

    申请号：US11091474

    申请日：2005-03-29

    Applicant: Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Yoshitaka Kamo

    Inventor： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Yoshitaka Kamo

    IPC: H01L21/28 ,  H01L21/338 ,  H01L29/417 ,  H01L29/778 ,  H01L29/80 ,  H01L29/812 ,  H01L31/072

    CPC classification number: H01L29/802

    Abstract: A heterojunction field effect transistor comprises a semi-insulating GaAs substrate, an n-InGaAs channel layer on the substrate, and a barrier layer on the n-InGaAs channel layer. The barrier layer is composed of a substantially fully depleted p-AlGaAs layer between two i-AlGaAs layers. A gate electrode is in Schottky contact with the barrier layer. Since the p-AlGaAs layer raises the barrier height in the barrier layer higher than the Schottky barrier, forward gate current is suppressed. In addition, the breakdown voltage is improved since a longer depletion region extends toward the drain side when a reverse bias is applied between the gate and the drain.

    Abstract translation: 异质结场效应晶体管包括半绝缘GaAs衬底，衬底上的n-InGaAs沟道层和n-InGaAs沟道层上的势垒层。 阻挡层由两个i-AlGaAs层之间的基本上完全耗尽的p-AlGaAs层组成。 栅电极与阻挡层肖特基接触。 由于p-AlGaAs层在阻挡层中提高了高于肖特基势垒的势垒高度，所以正向栅极电流被抑制。 此外，当在栅极和漏极之间施加反向偏压时，由于较长的耗尽区域朝着漏极侧延伸，所以击穿电压得到改善。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06307245B1

    公开(公告)日：2001-10-23

    申请号：US09479990

    申请日：2000-01-10

    Applicant: Tetsuo Kunii ,  Naohito Yoshida

    Inventor： Tetsuo Kunii ,  Naohito Yoshida

    IPC: H01L27095

    CPC classification number: H01L29/66871 ,  H01L21/28587 ,  H01L29/42316

    Abstract: A method of producing a semiconductor device includes a semiconductor substrate and a gate embedding layer. A pair of side walls made of insulating layers having a width are formed on the inner surface of a first opening and the gate embedding layer is formed by using the pair of side walls and a first insulating layer as masks so that the embedded portion and the first extending portion are self-aligned and, consequently, the first extending portion is symmetrical with respect to the embedded portion. Accordingly, the first extending portion of the gate electrode is offset toward the drain electrode or source electrode.

    Abstract translation: 一种制造半导体器件的方法包括半导体衬底和栅极嵌入层。 在第一开口的内表面上形成一对具有宽度的绝缘层制成的侧壁，并且通过使用一对侧壁和第一绝缘层作为掩模形成栅极嵌入层，使得嵌入部分和 第一延伸部分是自对准的，因此第一延伸部分相对于嵌入部分是对称的。 因此，栅电极的第一延伸部分朝向漏电极或源电极偏移。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110006351A1

    公开(公告)日：2011-01-13

    申请号：US12828328

    申请日：2010-07-01

    Applicant: Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    Inventor： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    IPC: H01L27/06 ,  H01L29/78 ,  H01L27/088

    CPC classification number: H01L29/4238 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/812

    Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

    Abstract translation: 半导体器件包括：半导体衬底; 在所述半导体衬底的顶表面处的杂质掺杂区域; 绝缘区域，位于半导体衬底的顶表面上的杂质掺杂区域周围; 杂质掺杂区上的栅电极; 位于所述杂质掺杂区域上的第一电极和第二电极，夹着所述栅电极; 位于所述绝缘区域上并连接到所述栅电极的第一焊盘; 在所述绝缘区域上跨越所述杂质掺杂区域面对所述第一焊盘的第二焊盘，并且连接到所述第二电极; 以及位于绝缘区域上的第一电极和第二焊盘之间的导体。

    Field-effect transistor
    6.
    发明授权
    Field-effect transistor 失效
    场效应晶体管

    公开(公告)号：US07557389B2

    公开(公告)日：2009-07-07

    申请号：US11557551

    申请日：2006-11-08

    Applicant: Hirotaka Amasuga ,  Tetsuo Kunii

    Inventor： Hirotaka Amasuga ,  Tetsuo Kunii

    IPC: H01L29/778

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/42316

    Abstract: A field-effect transistor includes a channel layer formed of a III-V compound semiconductor excluding aluminum; a gate contact layer formed of a III-V compound semiconductor and provided on the channel layer, the III-V compound semiconductor having a dopant concentration equal to or less than 1×1016 cm−3, containing aluminum, and having a large band gap energy; a gate buried layer of a III-V compound semiconductor and provided on the gate contact layer; and a gate electrode buried in the gate buried layer and in contact with the gate contact layer. A recess in the gate buried layer is opposed to an upper side wall of the gate electrode with a gap therebetween and a part of the gate buried layer, and where a contact with a lower side wall of the gate electrode is established, part of the gate buried layer remains without being removed.

    Abstract translation: 场效应晶体管包括由不包括铝的III-V族化合物半导体形成的沟道层; 由III-V族化合物半导体形成的栅极接触层，其设置在所述沟道层上，所述III-V族化合物半导体的掺杂剂浓度为1×10 16 cm -3以下，含有铝，并且具有大的带隙能量; 设置在栅极接触层上的III-V族化合物半导体的栅极掩埋层; 以及掩埋在栅极掩埋层中并与栅极接触层接触的栅电极。 栅极掩埋层中的凹部与栅电极的上侧壁相对，其间具有间隙，并且栅极掩埋层的一部分与栅电极的下侧壁的接触被建立， 栅极掩埋层保持不被去除。

    Field effect transistor
    7.
    发明授权
    Field effect transistor 有权
    场效应晶体管

    公开(公告)号：US07304329B2

    公开(公告)日：2007-12-04

    申请号：US10985057

    申请日：2004-11-10

    Applicant: Yoshitaka Kamo ,  Tetsuo Kunii

    Inventor： Yoshitaka Kamo ,  Tetsuo Kunii

    IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

    CPC classification number: H01L29/66871 ,  H01L29/41725 ,  H01L29/812

    Abstract: A field effect transistor includes a semiconductor substrate having an active region, a source region, and a drain region at an upper portion of the substrate. The active region is located between the source and drain regions. A gate electrode is located on the active region. A source electrode is located on the source region and forms an ohmic contact with the source region. A drain electrode has a base part on and in ohmic contact with the drain region and an extended part having edge close to the gate electrode and over a boundary between the active region and the drain region. An insulating film is located between the boundary and the extended part and has a thickness that increases along a direction from the drain electrode toward the gate electrode in a step-by-step or continuous manner.

    Abstract translation: 场效应晶体管包括在衬底的上部具有有源区，源极区和漏极区的半导体衬底。 有源区位于源区和漏区之间。 栅电极位于有源区上。 源电极位于源极区上并与源极区形成欧姆接触。 漏极电极具有与漏极区域基极和欧姆接触的基极部分，以及具有靠近栅极电极并且在有源区域和漏极区域之间的边界上的边缘的延伸部分。 绝缘膜位于边界和延伸部分之间，并且具有沿着从漏电极朝向栅电极的方向逐步或连续地增加的厚度。

    FIELD-EFFECT TRANSISTOR
    8.
    发明申请
    FIELD-EFFECT TRANSISTOR 失效
    场效应晶体管

    公开(公告)号：US20070267652A1

    公开(公告)日：2007-11-22

    申请号：US11557551

    申请日：2006-11-08

    Applicant: Hirotaka AMASUGA ,  Tetsuo KUNII

    Inventor： Hirotaka AMASUGA ,  Tetsuo KUNII

    IPC: H01L29/74

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/42316

    Abstract: A field-effect transistor includes a channel layer formed of a III-V compound semiconductor excluding aluminum; a gate contact layer formed of a III-V compound semiconductor and provided on the channel layer, the III-V compound semiconductor having a dopant concentration equal to or less than 1×1016 cm−3, containing aluminum, and having a large band gap energy; a gate buried layer of a III-V compound semiconductor and provided on the gate contact layer; and a gate electrode buried in the gate buried layer and in contact with the gate contact layer. A recess in the gate buried layer is opposed to an upper side wall of the gate electrode with a gap therebetween and a part of the gate buried layer, and where a contact with a lower side wall of the gate electrode is established, part of the gate buried layer remains without being removed.

    Abstract translation: 场效应晶体管包括由不包括铝的III-V族化合物半导体形成的沟道层; 由III-V族化合物半导体形成并设置在沟道层上的栅极接触层，掺杂剂浓度等于或小于1×10 16 cm -3的III-V族化合物半导体， / SUP>，含有铝，并具有大的带隙能量; 设置在栅极接触层上的III-V族化合物半导体的栅极掩埋层; 以及掩埋在栅极掩埋层中并与栅极接触层接触的栅电极。 栅极掩埋层中的凹部与栅电极的上侧壁相对，其间具有间隙，并且栅极掩埋层的一部分与栅电极的下侧壁的接触被建立， 栅极掩埋层保持不被去除。

    Semiconductor device and method of manufacturing the semiconductor device
    9.
    发明申请
    Semiconductor device and method of manufacturing the semiconductor device 失效
    半导体装置及其制造方法

    公开(公告)号：US20070132021A1

    公开(公告)日：2007-06-14

    申请号：US11445181

    申请日：2006-06-02

    Applicant: Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

    Inventor： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

    IPC: H01L29/76

    CPC classification number: H01L29/7783 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/8128

    Abstract: A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate electrode and a portion in the recess, other than where the gate electrode is located, and a shield electrode connected to the source electrode is located on a portion of the insulating film between the gate electrode and the drain electrode.

    Abstract translation: 半导体器件包括具有凹部的基板，在基板的凹部中的栅电极以及设置在栅电极的相对侧上的源电极和漏电极。 绝缘膜至少在栅电极的表面和凹部中的除了栅电极所在的部分之外的部分上，并且与源电极连接的屏蔽电极位于绝缘膜的一部分之间 栅电极和漏电极。

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