公开(公告)号：US20110006351A1

公开(公告)日：2011-01-13

申请号：US12828328

申请日：2010-07-01

申请人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

发明人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/4238 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/812

摘要： A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

摘要翻译： 半导体器件包括：半导体衬底; 在所述半导体衬底的顶表面处的杂质掺杂区域; 绝缘区域，位于半导体衬底的顶表面上的杂质掺杂区域周围; 杂质掺杂区上的栅电极; 位于所述杂质掺杂区域上的第一电极和第二电极，夹着所述栅电极; 位于所述绝缘区域上并连接到所述栅电极的第一焊盘; 在所述绝缘区域上跨越所述杂质掺杂区域面对所述第一焊盘的第二焊盘，并且连接到所述第二电极; 以及位于绝缘区域上的第一电极和第二焊盘之间的导体。

公开(公告)号：US08232609B2

公开(公告)日：2012-07-31

申请号：US12828328

申请日：2010-07-01

申请人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

发明人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

IPC分类号： H01L29/76

CPC分类号： H01L29/4238 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/812

摘要： A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

摘要翻译： 半导体器件包括：半导体衬底; 在所述半导体衬底的顶表面处的杂质掺杂区域; 绝缘区域，位于半导体衬底的顶表面上的杂质掺杂区域周围; 杂质掺杂区上的栅电极; 位于所述杂质掺杂区域上的第一电极和第二电极，夹着所述栅电极; 位于所述绝缘区域上并连接到所述栅电极的第一焊盘; 在所述绝缘区域上跨越所述杂质掺杂区域面对所述第一焊盘的第二焊盘，并且连接到所述第二电极; 以及位于所述绝缘区域上的所述第一电极和所述第二焊盘之间的导体。

公开(公告)号：US20070132021A1

公开(公告)日：2007-06-14

申请号：US11445181

申请日：2006-06-02

申请人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

发明人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

IPC分类号： H01L29/76

CPC分类号： H01L29/7783 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/8128

摘要： A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate electrode and a portion in the recess, other than where the gate electrode is located, and a shield electrode connected to the source electrode is located on a portion of the insulating film between the gate electrode and the drain electrode.

摘要翻译： 半导体器件包括具有凹部的基板，在基板的凹部中的栅电极以及设置在栅电极的相对侧上的源电极和漏电极。 绝缘膜至少在栅电极的表面和凹部中的除了栅电极所在的部分之外的部分上，并且与源电极连接的屏蔽电极位于绝缘膜的一部分之间 栅电极和漏电极。

公开(公告)号：US06911837B2

公开(公告)日：2005-06-28

申请号：US10893371

申请日：2004-07-19

申请人： Takahide Ishikawa ,  Yoshitsugu Yamamoto ,  Tetsuo Kunii ,  Satoshi Suzuki ,  Hirotaka Amasuga

发明人： Takahide Ishikawa ,  Yoshitsugu Yamamoto ,  Tetsuo Kunii ,  Satoshi Suzuki ,  Hirotaka Amasuga

IPC分类号： H01L21/288 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/66 ,  H01L23/66 ,  G01R31/26

CPC分类号： H01L22/22 ,  H01L21/485 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/00

摘要： The present method includes steps of: discharging a droplet of fluid containing fine particles with electric characteristics from an inkjet nozzle onto the microwave integrated circuit formed on a substrate; forming a coat of the fine particles having electric characteristics on the substrate; measuring electric characteristics of the microwave integrated circuit using a probe of a circuit evaluation apparatus before and after forming the coat; and adjusting the electric characteristics of the microwave integrated circuit, so that forming the coat at a desired location on the upper surface of the circuit substrate by scanning an aim of the inkjet nozzle against the circuit substrate enables the microwave integrated circuit to meet the specification.

摘要翻译： 本方法包括以下步骤：将含有电特性的细颗粒的液滴从喷墨喷嘴喷射到形成在基板上的微波集成电路上; 在基板上形成具有电特性的微粒的涂层; 使用电路评估装置的探针在形成涂层之前和之后测量微波集成电路的电特性; 并且调整微波集成电路的电特性，使得通过将喷墨喷嘴的目标扫过电路基板而在电路基板的上表面上的期望位置处形成涂层，使得微波集成电路能够满足规格。

公开(公告)号：US07528443B2

公开(公告)日：2009-05-05

申请号：US11445181

申请日：2006-06-02

申请人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

发明人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

IPC分类号： H01L29/778

CPC分类号： H01L29/7783 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/8128

摘要： A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate electrode and a portion in the recess, other than where the gate electrode is located, and a shield electrode connected to the source electrode is located on a portion of the insulating film between the gate electrode and the drain electrode.

摘要翻译： 半导体器件包括具有凹部的基板，在基板的凹部中的栅电极以及设置在栅电极的相对侧上的源电极和漏电极。 绝缘膜至少在栅电极的表面和凹部中的除了栅电极所在的部分之外的部分上，并且与源电极连接的屏蔽电极位于绝缘膜的一部分之间 栅电极和漏电极。

公开(公告)号：US20050046435A1

公开(公告)日：2005-03-03

申请号：US10893371

申请日：2004-07-19

申请人： Takahide Ishikawa ,  Yoshitsugu Yamamoto ,  Tetsuo Kunii ,  Satoshi Suzuki ,  Hirotaka Amasuga

发明人： Takahide Ishikawa ,  Yoshitsugu Yamamoto ,  Tetsuo Kunii ,  Satoshi Suzuki ,  Hirotaka Amasuga

IPC分类号： H01L21/288 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/66 ,  H01L23/66 ,  H01L29/06

CPC分类号： H01L22/22 ,  H01L21/485 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/00

摘要： The present method includes steps of: discharging a droplet of fluid containing fine particles with electric characteristics from an inkjet nozzle onto the microwave integrated circuit formed on a substrate; forming a coat of the fine particles having electric characteristics on the substrate; measuring electric characteristics of the microwave integrated circuit using a probe of a circuit evaluation apparatus before and after forming the coat; and adjusting the electric characteristics of the microwave integrated circuit, so that forming the coat at a desired location on the upper surface of the circuit substrate by scanning an aim of the inkjet nozzle against the circuit substrate enables the microwave integrated circuit to meet the specification.

摘要翻译： 本方法包括以下步骤：将含有电特性的细颗粒的液滴从喷墨喷嘴喷射到形成在基板上的微波集成电路上; 在基板上形成具有电特性的微粒的涂层; 使用电路评估装置的探针在形成涂层之前和之后测量微波集成电路的电特性; 并且调整微波集成电路的电特性，使得通过将喷墨喷嘴的目标扫过电路基板而在电路基板的上表面上的期望位置处形成涂层，使得微波集成电路能够满足规格。

公开(公告)号：US08878333B2

公开(公告)日：2014-11-04

申请号：US13545046

申请日：2012-07-10

申请人： Youichi Nogami ,  Hidetoshi Koyama ,  Yoshitsugu Yamamoto

发明人： Youichi Nogami ,  Hidetoshi Koyama ,  Yoshitsugu Yamamoto

IPC分类号： H01L21/70 ,  H01L23/482

CPC分类号： H01L23/4855 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.

摘要翻译： 半导体器件包括：具有主表面的半导体衬底; 主表面上的器件区域中的电极; 在主表面上的金属布线，并且具有连接到电极的第一端; 位于器件区域外部并与金属布线间隔开的电极焊盘; 主表面和主表面上的气隙形成膜之间的气隙，包围金属布线和电极的第一端，并具有第一开口; 封闭所述第一开口并覆盖所述金属布线的第二端的树脂; 相对于半导体衬底和气隙形成膜上的接触角，面向气隙的防液膜和当液体相对于树脂的接触角增大时， 以及通过位于树脂中的第二开口将金属布线连接到电极焊盘的金属膜。

公开(公告)号：US20050263788A1

公开(公告)日：2005-12-01

申请号：US11091474

申请日：2005-03-29

申请人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Yoshitaka Kamo

发明人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Yoshitaka Kamo

IPC分类号： H01L21/28 ,  H01L21/338 ,  H01L29/417 ,  H01L29/778 ,  H01L29/80 ,  H01L29/812 ,  H01L31/072

CPC分类号： H01L29/802

摘要： A heterojunction field effect transistor comprises a semi-insulating GaAs substrate, an n-InGaAs channel layer on the substrate, and a barrier layer on the n-InGaAs channel layer. The barrier layer is composed of a substantially fully depleted p-AlGaAs layer between two i-AlGaAs layers. A gate electrode is in Schottky contact with the barrier layer. Since the p-AlGaAs layer raises the barrier height in the barrier layer higher than the Schottky barrier, forward gate current is suppressed. In addition, the breakdown voltage is improved since a longer depletion region extends toward the drain side when a reverse bias is applied between the gate and the drain.

摘要翻译： 异质结场效应晶体管包括半绝缘GaAs衬底，衬底上的n-InGaAs沟道层和n-InGaAs沟道层上的势垒层。 阻挡层由两个i-AlGaAs层之间的基本上完全耗尽的p-AlGaAs层组成。 栅电极与阻挡层肖特基接触。 由于p-AlGaAs层在阻挡层中提高了高于肖特基势垒的势垒高度，所以正向栅极电流被抑制。 此外，当在栅极和漏极之间施加反向偏压时，由于较长的耗尽区域朝着漏极侧延伸，所以击穿电压得到改善。

公开(公告)号：US06570390B2

公开(公告)日：2003-05-27

申请号：US09941903

申请日：2001-08-29

申请人： Taisei Hirayama ,  Koichiro Ito ,  Ryo Hattori ,  Yoshitsugu Yamamoto ,  Yoshihiro Notani ,  Shinichi Miyakuni

发明人： Taisei Hirayama ,  Koichiro Ito ,  Ryo Hattori ,  Yoshitsugu Yamamoto ,  Yoshihiro Notani ,  Shinichi Miyakuni

IPC分类号： G01R3100

CPC分类号： G01N27/041 ,  G01N1/44

摘要： A method of measuring a surface leakage current includes applying a voltage between a pair of electrodes, which are apart from each other on a sample surface, during a predetermined period of time. A region of the sample surface between the pair of electrodes is irradiated by energy rays during an irradiation period of time which is within the voltage application time. The energy rays may be lasers, ultraviolet rays, X-rays or an electron beam. A current flowing between the pair of electrodes is measured during the voltage application time. The energy rays irradiation causes a surface leakage current, which is caused by adhered substances, to start to flow, and when the adhered substances have been eliminated perfectly, a relatively large current caused by the adhered substances disappears. Perfect elimination of the adhered substances can be verified by confirming that the relatively large current has disappeared.

公开(公告)号：US07700972B2

公开(公告)日：2010-04-20

申请号：US12143053

申请日：2008-06-20

申请人： Hideo Takeuchi ,  Yoshitsugu Yamamoto

发明人： Hideo Takeuchi ,  Yoshitsugu Yamamoto

IPC分类号： H01L29/205 ,  H01L29/778

CPC分类号： H01L27/0733 ,  H01L28/40 ,  H01L29/778

摘要： A semiconductor device comprises an AlN layer, a GaN layer, and an AlGaN layer sequentially formed on a semiconductor substrate. A first opening extends through said GaN layer and said AlGaN layer and exposes part of an upper surface of the AlN layer. A second opening extends through the semiconductor substrate and exposes a part of a lower surface of the AlN layer, in a location facing the first opening. A upper electrode is exposed on an upper surface of the AlN layer in the first opening; and a lower electrode is disposed on a lower surface of the AlN layer in the second opening.

摘要翻译： 半导体器件包括依次形成在半导体衬底上的AlN层，GaN层和AlGaN层。 第一开口延伸穿过所述GaN层和所述AlGaN层并暴露AlN层的上表面的一部分。 第二开口延伸穿过半导体衬底并且在面向第一开口的位置中暴露AlN层的下表面的一部分。 上电极暴露在第一开口中的AlN层的上表面上; 并且下电极设置在第二开口中的AlN层的下表面上。