公开(公告)号：US20070170589A1

公开(公告)日：2007-07-26

申请号：US11624386

申请日：2007-01-18

申请人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

发明人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

IPC分类号： H01L23/52 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11529

摘要： A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.

摘要翻译： 根据本发明的半导体集成电路包括由元件构成的单元阵列，具有布置在单元阵列上的线和空间的图案的导线，形成在导线上方的连接线，以及将导线 到连接线。 导线的一端侧从导体线之一顺序离开电池阵列的端部，接触孔布置在导线的一端侧，接触孔的尺寸较大 比导线的宽度大。

公开(公告)号：US07721239B2

公开(公告)日：2010-05-18

申请号：US11624386

申请日：2007-01-18

申请人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

发明人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

IPC分类号： G06F17/50

CPC分类号： G11C16/0483 ,  G11C16/08 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11529

摘要： A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.

摘要翻译： 根据本发明的半导体集成电路包括由元件构成的单元阵列，具有布置在单元阵列上的线和空间的图案的导线，形成在导线上方的连接线，以及将导线 到连接线。 导线的一端侧从导体线之一顺序离开电池阵列的端部，接触孔布置在导线的一端侧，接触孔的尺寸较大 比导线的宽度大。

公开(公告)号：US09129688B2

公开(公告)日：2015-09-08

申请号：US13608713

申请日：2012-09-10

申请人： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

发明人： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

IPC分类号： G11C16/16 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/16 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/1095

摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

摘要翻译： 根据一个实施例，形成在衬底中的第一导电类型的第一阱。 第二导电类型的第二阱形成在第一阱中。 多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是 布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

公开(公告)号：US08630106B2

公开(公告)日：2014-01-14

申请号：US12695623

申请日：2010-01-28

申请人： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

发明人： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

摘要翻译： 半导体存储器件包括存储单元单元，字线，驱动电路和第一晶体管。 字线连接到第0至第N个存储单元的控制栅极。 第（N + 1）个第一晶体管的数量分别将电压转移到字线。 将电压转移到第i个（i是0到N的范围内的自然数）字线的第一晶体管中的一个以上，靠近第i个字线的字线的M（M

公开(公告)号：US08243491B2

公开(公告)日：2012-08-14

申请号：US12884378

申请日：2010-09-17

申请人： Toshiki Hisada ,  Hiromitsu Mashita

发明人： Toshiki Hisada ,  Hiromitsu Mashita

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C7/18 ,  G11C2207/002 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.

摘要翻译： 根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。 位线包括顺序排列的第一，第二，第三和第四位线。 第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。 第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。 第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。 第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。

公开(公告)号：US20120001331A1

公开(公告)日：2012-01-05

申请号：US13051652

申请日：2011-03-18

申请人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

发明人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

IPC分类号： H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76816 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.

摘要翻译： 根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。 多个第一互连周期性地布置成在一个方向上延伸。 第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。 第三互连设置在组和第二互连之间。 多个导电构件设置在从第二互连件观察的与组相反的一侧上。 第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。 第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。

公开(公告)号：US20130003461A1

公开(公告)日：2013-01-03

申请号：US13608713

申请日：2012-09-10

申请人： Katsuaki ISOBE ,  Noboru Shibata ,  Toshiki Hisada

发明人： Katsuaki ISOBE ,  Noboru Shibata ,  Toshiki Hisada

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/1095

摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

摘要翻译： 根据一个实施例，形成在衬底中的第一导电类型的第一阱。 第二导电类型的第二阱形成在第一阱中。 多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是 布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

公开(公告)号：US08243524B2

公开(公告)日：2012-08-14

申请号：US12723864

申请日：2010-03-15

申请人： Yuya Suzuki ,  Toshiki Hisada ,  Yoshikazu Hosomura

发明人： Yuya Suzuki ,  Toshiki Hisada ,  Yoshikazu Hosomura

IPC分类号： G11C16/06

CPC分类号： G11C8/10 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526

摘要： A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection.

摘要翻译： 半导体存储装置具有读出放大器。 读出放大器包括第一下部互连; 形成在第一层间绝缘膜上的第二层间绝缘膜和第一互连的顶部; 形成在与半导体衬底的衬底平面垂直的方向上以便穿过第二层间绝缘膜并且连接到第一下互连的接触互连; 形成在所述第二层间绝缘膜上并连接到设置在所述第一上部互连件下方的所述接触互连的第一上互连; 在第二层间绝缘膜中与垂直于半导体衬底的衬底平面的方向形成的虚拟接触互连，并且与接触互连相邻; 以及形成在所述第二层间绝缘膜上以沿所述第一方向延伸的第二上部互连件，并且连接到设置在所述第二上部互连件下方的所述虚拟接触互连件。

公开(公告)号：US20110134695A1

公开(公告)日：2011-06-09

申请号：US12957865

申请日：2010-12-01

申请人： Kazushige Kanda ,  Toshiki Hisada ,  Katsuaki Isobe

发明人： Kazushige Kanda ,  Toshiki Hisada ,  Katsuaki Isobe

IPC分类号： G11C16/04

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.

摘要翻译： 提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于 低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

公开(公告)号：US06928596B2

公开(公告)日：2005-08-09

申请号：US09948406

申请日：2001-09-06

申请人： Tohru Kimura ,  Toshiki Hisada

发明人： Tohru Kimura ,  Toshiki Hisada

IPC分类号： G01R31/28 ,  G06F12/16 ,  G11C29/12 ,  G11C29/46 ,  G11C29/48 ,  G11C29/00

CPC分类号： G11C29/48 ,  G11C29/46

摘要： A test code is input to a test mode control circuit so that the test mode control circuit creates the test decode signal. The test decode signal is converted into serial data with a parallel·serial converting circuit in synchronization with a base clock. The serial data is input to a serial·parallel converting circuit located in the vicinity of the test code latch circuit dispersed on the semiconductor chip via one very long serial data line extending from end to end of the semiconductor chip.

摘要翻译： 将测试代码输入到测试模式控制电路，使得测试模式控制电路创建测试解码信号。 测试解码信号与基准时钟同步的并行转换电路转换为串行数据。 串行数据通过从半导体芯片的端到端延伸的一个非常长的串行数据线输入到分散在半导体芯片上的测试代码锁存电路附近的串行并行转换电路。