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1.发明授权ESD protection using a capacitivly-coupled clamp for protecting low-voltage core transistors from high-voltage outputs 有权使用电容耦合钳位保护低压核心晶体管免受高压输出的ESD保护公开(公告)号：US08072721B2
公开(公告)日：2011-12-06
申请号：US12481696
申请日：2009-06-10
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K19/018557
摘要： An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.
摘要翻译： 静电放电（ESD）保护电路保护核心晶体管。 n沟道输出晶体管的栅极的内部节点连接到n沟道栅极 - 接地晶体管的漏极到地。 栅极接地晶体管的栅极是通过ESD耦合电容器耦合到输出并由n沟道禁用晶体管和漏电阻器接地的耦合栅极节点。 n沟道禁用晶体管的栅极连接电源，并在供电时禁用ESD保护电路。 施加到输出端的ESD脉冲通过ESD耦合电容器耦合，使耦合栅极节点高电压，并接通栅极 - 接地晶体管，使n沟道输出晶体管的栅极接地，从而分解ESD电流。 防止ESD脉冲通过栅极接地晶体管的n沟道输出晶体管的寄生米勒电容器耦合。
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2.发明授权Constant-current control module using inverter filter multiplier for off-line current-mode primary-side sense isolated flyback converter 有权恒流控制模块采用变频器滤波器，用于离线电流模式初级侧感测隔离反激式转换器公开(公告)号：US08300431B2
公开(公告)日：2012-10-30
申请号：US12718707
申请日：2010-03-05
申请人： Chik Wai (David) Ng , Hing Kit Kwan , Po Wah (Patrick) Chang , Wai Kit (Victor) So , Kwok Kuen (David) Kwong
发明人： Chik Wai (David) Ng , Hing Kit Kwan , Po Wah (Patrick) Chang , Wai Kit (Victor) So , Kwok Kuen (David) Kwong
IPC分类号： H02M3/335
CPC分类号： H02M3/335
摘要： A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.
摘要翻译： 回扫AC-DC电力转换器具有恒定电流控制回路，其感测变压器中的主要输出电流，以在没有昂贵的光隔离器的情况下控制次级输出。 初级侧控制电路可以使用准谐振（QR）或脉冲宽度调制（PWM）控制回路来切换通过变压器的一次电流的开和关。 将反馈电压与从初级电流回路感测的初级侧电压进行比较，以打开和关闭开关。 乘法器环路使用乘法器产生反馈电压。 电平移位反相器和低通滤波器通过将开关的占空比乘以反馈电压作为乘法器，以产生滤波电压。 高增益误差放大器将滤波电压与参考电压进行比较，以产生反馈电压。 乘法器产生二次电流和参考电压之间的简单关系，产生简化的电流控制。
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3.发明申请Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter 有权恒流控制模块使用变频滤波乘法器进行离线电流模式初级侧检测隔离反激式转换器公开(公告)号：US20110216559A1
公开(公告)日：2011-09-08
申请号：US12718707
申请日：2010-03-05
IPC分类号： H02M3/335
CPC分类号： H02M3/335
摘要： A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.
摘要翻译： 回扫AC-DC电力转换器具有恒定电流控制回路，其感测变压器中的主要输出电流，以在没有昂贵的光隔离器的情况下控制次级输出。 初级侧控制电路可以使用准谐振（QR）或脉冲宽度调制（PWM）控制回路来切换通过变压器的一次电流的开和关。 将反馈电压与从初级电流回路感测的初级侧电压进行比较，以打开和关闭开关。 乘法器环路使用乘法器产生反馈电压。 电平移位反相器和低通滤波器通过将开关的占空比乘以反馈电压作为乘法器，以产生滤波电压。 高增益误差放大器将滤波电压与参考电压进行比较，以产生反馈电压。 乘法器产生二次电流和参考电压之间的简单关系，产生简化的电流控制。
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4.发明授权公开(公告)号：US07017097B1
公开(公告)日：2006-03-21
申请号：US10253960
申请日：2002-09-24
申请人： Michael T. Moore , Victor So , Pankaj K. Jha
发明人： Michael T. Moore , Victor So , Pankaj K. Jha
IPC分类号： G01R31/28
CPC分类号： G01R31/318364 , G01R31/318328
摘要： An apparatus generally comprising a circuit and an interface device is disclosed. The circuit may be configured to (i) generate a plurality of test signals to simultaneously stimulate a device and a model of the device during a test and (ii) receive a plurality of model signals generated by the model in response to the test signals. The interface device may be configured to receive a plurality of device signals generated by the device in response the test signals.
摘要翻译： 公开了一种通常包括电路和接口装置的装置。 电路可以被配置为（i）产生多个测试信号，以在测试期间同时刺激设备和模型，以及（ii）响应于测试信号接收由模型产生的多个模型信号。 接口设备可以被配置为响应于测试信号而接收由设备产生的多个设备信号。
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5.发明授权
公开(公告)号：US5428252A
公开(公告)日：1995-06-27
申请号：US817465
申请日：1992-01-03
申请人： Andre B. Walker , Victor So
发明人： Andre B. Walker , Victor So
CPC分类号： G11C5/141 , G06F1/30 , H02J9/061 , Y10T307/615
摘要： A microcontroller power management system wherein the voltage of a power supply is monitored and the microcontroller central processing unit ("CPU") receives an interrupt signal when the supply voltage falls below a predetermined level. The CPU monitors the duration of the low voltage condition and switches into a sleep mode, after storing any data in its registers that are not maintained in the sleep mode, when that duration exceeds a fixed limit that indicates more than a temporary power glitch is being experienced. If only a short power glitch, the CPU continues normal operation. A large capacitor connected to the power supply input to the microcontroller provides enough energy for the microcontroller to operate normally during short glitches and to operate in a sleep mode for a considerable time, thereby maintaining data in CMOS static RAM until power is restored. This is particularly useful for battery operated systems, responding to both a low battery voltage condition and to a complete loss of power during battery replacement.
摘要翻译： 一种微处理器电源管理系统，其中监视电源的电压，并且当电源电压低于预定电平时，微控制器中央处理单元（“CPU”）接收中断信号。 在将任何数据存储在不保持在睡眠模式的寄存器中时，CPU将监视低电压状态的持续时间并切换到休眠模式，当该持续时间超过指示超过临时电源故障的固定限制时 有经验的。 如果只有短暂的电源故障，CPU会继续正常运行。 连接到微控制器的电源输入的大电容器提供足够的能量，以使微控制器在短时间毛刺期间正常工作并在睡眠模式下工作相当长的时间，从而在电源恢复之前保持CMOS静态RAM中的数据。 这对于电池供电的系统特别有用，对电池电压低的条件和电池更换期间电源的完全损失做出回应。
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6.发明授权Output current estimation for an isolated flyback converter with variable switching frequency control and duty cycle adjustment for both PWM and PFM modes 有权用于PWM和PFM模式的具有可变开关频率控制和占空比调整的隔离反激式转换器的输出电流估计公开(公告)号：US08780590B2
公开(公告)日：2014-07-15
申请号：US13462986
申请日：2012-05-03
IPC分类号： H02M3/335
CPC分类号： H02M3/33507 , H02M2001/0009
摘要： A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching.
摘要翻译： 回扫功率转换器具有电流估算控制回路，其感测变压器中的主要输出电流以控制次级输出。 初级侧控制电路通过变压器开启和关闭一次电流。 通过变压器的辅助绕组的二次电流流过的放电时间是通过对用于拐点的辅助回路上的分压器进行采样而产生的。 通过将放电时间乘以与开关频率成比例的电流并与具有开关频率的锯齿波信号进行比较来计算归一化占空比。 初级侧电压的峰值从初级电流回路感测并转换为电流并乘以归一化的占空比以产生估计电流。 误差放大器将估计电流与参考值进行比较，以调整振荡器频率和峰值电流以控制主开关。
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7.发明授权Programmable electro-magnetic-interference (EMI) reduction with enhanced noise immunity and process tolerance 有权可编程电磁干扰（EMI）降低，增强抗噪声和工艺容差公开(公告)号：US08188798B1
公开(公告)日：2012-05-29
申请号：US12948896
申请日：2010-11-18
申请人： Chi Tak (Gerry) Leung , Chik Wai (David) Ng , Hing Kit Kwan , Wai Kit (Victor) So , Po Wah (Patrick) Chang , Wing Cheong Mak , Kwok Kuen (David) Kwong
发明人： Chi Tak (Gerry) Leung , Chik Wai (David) Ng , Hing Kit Kwan , Wai Kit (Victor) So , Po Wah (Patrick) Chang , Wing Cheong Mak , Kwok Kuen (David) Kwong
CPC分类号： H03L7/08
摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.
摘要翻译： 频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。 该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。 减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。 当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。 由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。 可以通过对减法器中的反馈电阻进行编程来调整抖动度。 减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。
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8.发明申请Output Current Estimation for an Isolated Flyback Converter With Variable Switching Frequency Control and Duty Cycle Adjustment for Both PWM and PFM Modes 有权用于PWM和PFM模式的具有可变开关频率控制和占空比调整的隔离反激式转换器的输出电流估计公开(公告)号：US20130294118A1
公开(公告)日：2013-11-07
申请号：US13462986
申请日：2012-05-03
CPC分类号： H02M3/33507 , H02M2001/0009
摘要： A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching.
摘要翻译： 回扫功率转换器具有电流估算控制回路，其感测变压器中的主要输出电流以控制次级输出。 初级侧控制电路通过变压器开启和关闭一次电流。 通过变压器的辅助绕组的二次电流流过的放电时间是通过对用于拐点的辅助回路上的分压器进行采样而产生的。 通过将放电时间乘以与开关频率成比例的电流并与具有开关频率的锯齿波信号进行比较来计算归一化占空比。 初级侧电压的峰值从初级电流回路感测并转换为电流并乘以归一化占空比以产生估计电流。 误差放大器将估计电流与参考值进行比较，以调整振荡器频率和峰值电流以控制主开关。
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9.发明申请PROGRAMMABLE ELECTRO-MAGNETIC-INTERFERENCE (EMI) REDUCTION WITH ENHANCED NOISE IMMUNITY AND PROCESS TOLERANCE 有权可编程电磁干扰（EMI）减少与增强的噪声免疫和过程公差公开(公告)号：US20120126901A1
公开(公告)日：2012-05-24
申请号：US12948896
申请日：2010-11-18
申请人： Chi Tak (Gerry) LEUNG , Chik Wai (David) NG , Hing Kit KWAN , Wai Kit (Victor) SO , Po Wah CHANG , Wing Cheong MAK , Kwok Kuen KWONG
发明人： Chi Tak (Gerry) LEUNG , Chik Wai (David) NG , Hing Kit KWAN , Wai Kit (Victor) SO , Po Wah CHANG , Wing Cheong MAK , Kwok Kuen KWONG
IPC分类号： H03L7/00
CPC分类号： H03L7/08
摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.
摘要翻译： 频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。 该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。 减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。 当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。 由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。 可以通过对减法器中的反馈电阻进行编程来调整抖动度。 减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。
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10.发明申请ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs 有权使用电容耦合钳位保护低压芯片晶体管的ESD保护从高压输出公开(公告)号：US20100315748A1
公开(公告)日：2010-12-16
申请号：US12481696
申请日：2009-06-10
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K19/018557
摘要： An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.
摘要翻译： 静电放电（ESD）保护电路保护核心晶体管。 n沟道输出晶体管的栅极的内部节点连接到n沟道栅极 - 接地晶体管的漏极到地。 栅极接地晶体管的栅极是通过ESD耦合电容器耦合到输出并由n沟道禁用晶体管和漏电阻器接地的耦合栅极节点。 n沟道禁用晶体管的栅极连接电源，并在供电时禁用ESD保护电路。 施加到输出端的ESD脉冲通过ESD耦合电容器耦合，使耦合栅极节点高电压，并接通栅极 - 接地晶体管，使n沟道输出晶体管的栅极接地，从而分解ESD电流。 防止ESD脉冲通过栅极接地晶体管的n沟道输出晶体管的寄生米勒电容器耦合。
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