公开(公告)号：US5704039A

公开(公告)日：1997-12-30

申请号：US632179

申请日：1996-04-15

申请人： Oded Yishay ,  William P. LaViolette ,  Daniel W. Pechonis

发明人： Oded Yishay ,  William P. LaViolette ,  Daniel W. Pechonis

IPC分类号： G06F11/28 ,  G06F12/14 ,  G06F21/22 ,  G11C7/24 ,  G11C8/20 ,  G06F11/00

CPC分类号： G06F12/1466 ,  G11C7/24 ,  G11C8/20

摘要： A data processing system (10) allows an authorized user to unlock a security mode by providing a code stored in a plurality of mask registers (60,62,66) such that the system is selectively allowed to communicate with an external device. When an reset signal is received, a selector (48) selects a first mask register (60) and retrieves a first stored address value and a first stored data value therefrom. The first stored address and data values are respectively compared with a first address value and a first data value by a comparator (44). This process of selecting and comparing continues until a final match signal is asserted. When the final match signal is asserted, a secure signal is negated and the system may communicate with the external user.

摘要翻译： 数据处理系统（10）允许授权用户通过提供存储在多个屏蔽寄存器（60,62,66）中的代码来解锁安全模式，使得系统被选择性地允许与外部设备通信。 当接收到复位信号时，选择器（48）选择第一屏蔽寄存器（60）并且从中检索第一存储的地址值和第一存储的数据值。 第一存储的地址和数据值分别通过比较器（44）与第一地址值和第一数据值进行比较。 该选择和比较的过程继续进行，直到最终匹配信号被断言为止。 当最终匹配信号被断言时，安全信号被否定，并且系统可以与外部用户通信。

公开(公告)号：US5448744A

公开(公告)日：1995-09-05

申请号：US432423

申请日：1989-11-06

申请人： James B. Eifert ,  John J. Vaglica ,  James C. Smallwood ,  Mark W. McDermott ,  Hiroyuki Sugiyama ,  William P. LaViolette ,  Bradley G. Burgess

发明人： James B. Eifert ,  John J. Vaglica ,  James C. Smallwood ,  Mark W. McDermott ,  Hiroyuki Sugiyama ,  William P. LaViolette ,  Bradley G. Burgess

IPC分类号： G06F9/38 ,  G06F9/22 ,  G06F13/10

CPC分类号： G06F9/3877

摘要： An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.

摘要翻译： 集成电路微处理器具有板载可编程芯片选择逻辑。 几个芯片选择输出中的每一个可以通过一个或多个控制寄存器位字段单独编程。 例如，每个芯片选择在起始地址和块大小均可编程的地址范围内被断言用于总线周期。 此外，每个芯片选择都可以被编程为仅在读周期有效，仅在写周期或读周期和写周期。 只有在确认中断与该芯片选择相同的优先级时，每个芯片选择才能在中断确认周期内被编程为有效。 此外，每个芯片选择的断言的定时可编程为与总线周期的地址选通或数据选通一致。 芯片选择逻辑被设计为使得其被配置为在复位之后由处理器运行的第一总线周期期间产生有效芯片选择信号而退出复位。 该芯片选择适用于选择引导ROM，然后可以重新编程以供其他使用。 芯片选择逻辑能够通过断言适当的周期终止信号来支持逐周期动态总线大小调整。 芯片选择逻辑还可以将可编程的等待状态数插入总线周期以适应慢速外设，或者可能导致总线周期的快速终止，从而提高快速外设的利用率。

公开(公告)号：US5166685A

公开(公告)日：1992-11-24

申请号：US850256

申请日：1992-03-12

申请人： Jules D. Campbell, Jr. ,  William D. Huston ,  William P. Laviolette

发明人： Jules D. Campbell, Jr. ,  William D. Huston ,  William P. Laviolette

IPC分类号： G06F3/05 ,  H03M1/12

CPC分类号： H03M1/12 ,  G06F3/05

摘要： An analog-to-digital conversion system module comprises a pin-limited A/D converter integrated circuit (I.C.) to which at least one multiplexer I.C. may be coupled and sampled.In one embodiment, host system software involvement is minimized by providing a sequence of sample commands, implemented by a channel sequencer or a programmable control table comprising a plurality of conversion command words (CCW's). A set of CCW's defines a conversion sequence which may be initiated and performed with minimal host system software involvement, upon conclusion of which a result table storing the converted digital values may be read by an associated device, such as a CPU.In one embodiment, some I/O pins of the A/D converter I.C. function either as analog inputs or address outputs to the external multiplexer, while other analog input pins alternatively function as single input channels or as combined channels from one or more external multiplexers. A software-loadable control register comprises a control field for a control word which determines the function of the programmable pins.

摘要翻译： 一个模数转换系统模块包括一个引脚限制的A / D转换器集成电路（I.C.），至少一个多路复用器I.C。 可以被耦合和采样。 在一个实施例中，通过提供由信道定序器或包括多个转换命令字（CCW's）的可编程控制表实现的采样命令序列来最小化主机系统软件参与。 一组CCW定义了可以以最少的主机系统软件参与来启动和执行的转换序列，其结论是存储转换的数字值的结果表可以由诸如CPU的相关联的设备读取。 在一个实施例中，A / D转换器I.C的一些I / O引脚。 作为模拟输入或地址输出到外部多路复用器，而其他模拟输入引脚可以作为单个输入通道或来自一个或多个外部多路复用器的组合通道。 软件可加载控制寄存器包括用于确定可编程引脚功能的控制字的控制字段。

公开(公告)号：US4602327A

公开(公告)日：1986-07-22

申请号：US518494

申请日：1983-07-28

申请人： William P. LaViolette ,  David S. Mothersole ,  John Zolnowsky

发明人： William P. LaViolette ,  David S. Mothersole ,  John Zolnowsky

IPC分类号： G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A bus master is provided with the capability to accept a data transfer task from a CPU, which includes the performance of a predetermined sequence of data transfer operations between memory and a selected peripheral controlled by a respective controller. During any one of the operations, the bus master may be requested to relinquish the bus so that a higher priority transfer may occur or a deadlock condition resolved. In response to such request, the bus master immediately terminates the current bus cycle, but remembers the state thereof at the time of relinquishment. After the high priority transfer is completed, the bus master may be allowed to rearbitrate for use of the bus. Upon again obtaining control of the bus, the bus master restarts the bus cycle which was prematurely terminated and continues the sequence of operations as if no relinquishment had occurred.

摘要翻译： 总线主机被提供接受来自CPU的数据传输任务的能力，其包括执行存储器和由相应控制器控制的所选外围设备之间的预定数据传送操作序列。 在任何一个操作期间，可能要求总线主机放弃总线，以便可能发生更高优先级的传输或解决死锁状态。 响应于这样的请求，总线主机立即终止当前总线周期，但是在放弃时记住它的状态。 高优先级传输完成后，总线主机可以被允许对总线进行后台处理。 在再次获得对总线的控制时，总线主机重新启动了过早终止的总线周期，并继续执行操作，就好像没有放弃发生。

公开(公告)号：US5155451A

公开(公告)日：1992-10-13

申请号：US835834

申请日：1992-02-18

申请人： Michael E. Gladden ,  William P. LaViolette

发明人： Michael E. Gladden ,  William P. LaViolette

IPC分类号： G06F1/06 ,  G06F15/78 ,  H03L7/089 ,  H03L7/10 ,  H03L7/14 ,  H03L7/18 ,  H03L7/183

CPC分类号： H03L7/183 ,  H03L7/10 ,  H03L7/14 ,  H03L7/0891

摘要： A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.