公开(公告)号：US07923359B1

公开(公告)日：2011-04-12

申请号：US11576344

申请日：2005-09-28

申请人： Wolfgang Euen ,  Stephan Gross

发明人： Wolfgang Euen ,  Stephan Gross

IPC分类号： H01L21/425

CPC分类号： H01L21/32155 ,  H01L21/26506 ,  H01L21/28035 ,  H01L29/4916

摘要： There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.

摘要翻译： 存在一种降低注入磷的多晶硅的薄层电阻的方法。 在示例性实施例中，存在MOS晶体管结构。 该结构具有栅极区，漏极区和源极区。 减小栅极区域的薄层电阻的方法包括将预定温度的本征非晶硅沉积到栅极区上。 将非晶化物种植入本征非晶硅中。 然后将磷物质注入MOS晶体管结构的栅极区域。 该实施方案的特征包括使用Ar +作为非晶化物质。

公开(公告)号：US4869781A

公开(公告)日：1989-09-26

申请号：US259082

申请日：1988-10-17

申请人： Wolfgang Euen ,  Dieter Hagmann ,  Hans-Joachim Trumpp

发明人： Wolfgang Euen ,  Dieter Hagmann ,  Hans-Joachim Trumpp

IPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32105 ,  H01L21/32137 ,  Y10S257/90 ,  Y10S438/947 ,  Y10S438/95

摘要： A method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate to define regions which are designated to contain devices. A first insulating compound layer is formed on the surface of the semiconductor substrate which is designated to be in part the gate dielectric. Subsequently, a polycrystalline silicon layer is deposited onto the compound layer. The polycrystalline silicon layer is heavily doped by phosphorus ion implantation and annealed below about 850.degree. C. Polycrystalline silicon portions are delineated by photolithography and dry etching. Dry etching is carried out in SF.sub.6 -Cl.sub.2 /He at a low power density of about 0.1 to 0.3 watts/cm.sup.2. The remaining portions of polycrystalline silicon layer are subjected to a thermal oxidation at a temperature of about 800.degree. C. during which controllable quantities of the polycrystalline silicon are consumed. After removal of the thermally grown oxide, polycrystalline silicon portions are obtained with length and thickness dimensions reduced by a desired amount. If polycrystalline silicon portions are to be reduced only in length, the horizontal surfaces of these portions are protected during oxidation by a cap. The cap may include a several nm thick silicon nitride layer which is arranged on a silicon dioxide stress-relieve layer. The method is particularly useful in forming a submicrometer length gate electrode of a field effect transistor.

摘要翻译： 描述了一种用于制造具有亚微米长度器件元件的半导体集成电路结构的方法，其中在半导体衬底中形成表面隔离图案以限定被指定为容纳器件的区域。 第一绝缘化合物层形成在半导体衬底的被指定为部分栅极电介质的表面上。 随后，在化合物层上沉积多晶硅层。 多晶硅层通过磷离子注入重掺杂并在约850℃以下退火。多晶硅部分通过光刻和干法刻蚀来描绘。 在SF6-Cl2 / He中以约0.1至0.3瓦特/平方厘米的低功率密度进行干蚀刻。 多晶硅层的剩余部分在约800℃的温度下进行热氧化，在此期间消耗可控量的多晶硅。 在去除热生长的氧化物之后，获得长度和厚度尺寸减小期望量的多晶硅部分。 如果仅在长度上减少多晶硅部分，则这些部分的水平表面在通过盖子氧化时被保护。 盖可以包括布置在二氧化硅应力释放层上的数nm厚的氮化硅层。 该方法在形成场效应晶体管的亚微米长栅极电极时特别有用。

公开(公告)号：US5268311A

公开(公告)日：1993-12-07

申请号：US691256

申请日：1991-04-25

申请人： Wolfgang Euen ,  Dieter Hagmann ,  Hans-Jurgen Wildau

发明人： Wolfgang Euen ,  Dieter Hagmann ,  Hans-Jurgen Wildau

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/265

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/3105

摘要： Disclosed is a thin dielectric inorganic layer overlaying a substrate, and having a thickness of.ltoreq. about 20 nm and a defect density of.ltoreq. about 0.6 defects/cm.sup.2 determined by BV measurements.Also disclosed is a method of forming such a layer, according to which a layer having the desired composition and thickness is formed on a substrate, followed by an ion implantation into the substrate through the layer with a dose of.gtoreq. about 10.sup.15 ions/cm.sup.2 and a subsequent anneal at a temperature of.gtoreq. about 500.degree. C. for a predetermined time.

摘要翻译： 公开了覆盖基板的薄介电无机层，其厚度为约20nm，通过BV测量确定的缺陷密度为约0.6缺陷/ cm2。 还公开了一种形成这种层的方法，根据该方法，在衬底上形成具有所需组成和厚度的层，然后通过层以离子注入到衬底中，剂量为≥1015个离子/ cm2，然后在> 500℃左右的温度下进行预定时间的退火。

公开(公告)号：US5139869A

公开(公告)日：1992-08-18

申请号：US686086

申请日：1991-04-16

申请人： Wolfgang Euen ,  Dieter Hagmann ,  Hans J. Wildau

发明人： Wolfgang Euen ,  Dieter Hagmann ,  Hans J. Wildau

IPC分类号： H01L21/28 ,  H01L21/3105

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/3105 ,  Y10T428/265

摘要： Disclosed is a thin dielectric inorganic layer overlaying a substrate, and having a thickness of .ltoreq. about 20 nm and a defect density of .ltoreq. about 0.6 defects/cm.sup.2 determined by BV measurements.Also disclosed is a method of forming such a layer, according to which a layer having the desired composition and thickness is formed on a substrate, followed by an ion implantation into the substrate through the layer with a dose of .gtoreq. about 10.sup.15 ions/cm.sup.2 and a subsequent anneal at a temperature of .gtoreq. about 500.degree. C. for a predetermined time.

摘要翻译： 公开了覆盖基板的薄介电无机层，其厚度为约20nm，通过BV测量确定的缺陷密度为约0.6缺陷/ cm2。 还公开了一种形成这种层的方法，根据该方法，在衬底上形成具有所需组成和厚度的层，然后通过层以离子注入到衬底中，剂量为≥1015个离子/ cm2，然后在> 500℃左右的温度下进行预定时间的退火。

公开(公告)号：US20100001322A1

公开(公告)日：2010-01-07

申请号：US12088733

申请日：2006-10-05

申请人： Wolfgang Euen ,  Holger Schligtenhorst ,  Rainer Bauer ,  Marc Van Geffen ,  Karl-Heinz Kraft

发明人： Wolfgang Euen ,  Holger Schligtenhorst ,  Rainer Bauer ,  Marc Van Geffen ,  Karl-Heinz Kraft

IPC分类号： H01L21/762 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L21/76254 ,  H01L27/1266 ,  H01L29/66772

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising silicon which is provided with at least one semiconductor element (T), wherein an epitaxial semiconductor layer (1) comprising silicon is grown on top of a first semiconductor substrate (14), wherein a splitting region (2) is formed in the epitaxial layer (1), wherein a second substrate (11) is attached by wafer bonding to the first substrate (12) at the side of the epitaxial layer (1) provided with the splitting region (2) while an electrically insulating region (3) is interposed between the epitaxial layer (1) and the second substrate (11), the structure thus formed is split at the location of the splitting region (2) as a result of which the second substrate (11) forms the substrate (11) with on top of the insulating region (3) a part (IA) of the epitaxial layer forming the semiconductor body (12) in which the semiconductor element (T) is formed. According to the invention for the thickness of the epitaxial layer (1) a thickness is chosen that is larger than about 3 μm. Preferably, the thickness is chosen between 5 and 15 μm. Best results are obtained with a thickness in the range of 7 to 13 μm. Devices 10, in particular high-voltage FETs, are obtained easily and with high yield and uniform properties like leakage current. The invention also comprises a method of manufacturing an SOI structure 12 and an SOI structure 12 thus obtained.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和包括硅的半导体本体（12），所述半导体器件（12）设置有至少一个半导体元件（T），其中外延半导体层（1） 包括硅生长在第一半导体衬底（14）的顶部，其中在所述外延层（1）中形成分裂区域（2），其中通过晶片接合将第二衬底（11）附接到所述第一衬底（12） ）在设置有分离区域（2）的外延层（1）的侧面，同时电绝缘区域（3）插入在外延层（1）和第二基板（11）之间，由此形成的结构被分裂 在分离区域（2）的位置处，第二衬底（11）在绝缘区域（3）的顶部上形成衬底（11），形成半导体本体的外延层的一部分（IA） （12），其中形成半导体元件（T） ed。 根据本发明，对于外延层（1）的厚度，选择大于约3μm的厚度。 优选地，厚度选择在5和15μm之间。 获得最佳结果，其厚度在7至13μm的范围内。 器件10，特别是高电压FET，容易获得并具有高产率和均匀的性能，如漏电流。 本发明还包括制造如此获得的SOI结构12和SOI结构12的方法。

公开(公告)号：US20110097883A1

公开(公告)日：2011-04-28

申请号：US11576344

申请日：2005-09-28

申请人： Wolfgang Euen ,  Stephan Gross

发明人： Wolfgang Euen ,  Stephan Gross

IPC分类号： H01L21/28

CPC分类号： H01L21/32155 ,  H01L21/26506 ,  H01L21/28035 ,  H01L29/4916

摘要： There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.

摘要翻译： 存在一种降低注入磷的多晶硅的薄层电阻的方法。 在示例性实施例中，存在MOS晶体管结构。 该结构具有栅极区，漏极区和源极区。 减小栅极区域的薄层电阻的方法包括将预定温度的本征非晶硅沉积到栅极区上。 将非晶化物种植入本征非晶硅中。 然后将磷物质注入MOS晶体管结构的栅极区域。 该实施方案的特征包括使用Ar +作为非晶化物质。

公开(公告)号：US5051377A

公开(公告)日：1991-09-24

申请号：US400300

申请日：1989-08-29

申请人： Wolfgang Euen ,  Dieter Hagmann ,  Hans-Jurgen Wildau

发明人： Wolfgang Euen ,  Dieter Hagmann ,  Hans-Jurgen Wildau

IPC分类号： C23C14/06 ,  C23C14/08 ,  C23C14/10 ,  C23C14/48 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/822 ,  H01L27/04

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/3105 ,  Y10S438/91

摘要： Disclosed is a thin dielectric inorganic layer overlaying a substrate, and having a thickness of .ltoreq. about 20 nm and a defect density of .ltoreq. about 0.6 defects/cm.sup.2 determined by BV measurements.Also disclosed is a method of forming such a layer, according to which a layer having the desired composition and thickness is formed on a substrate, followed by an ion implanatation into the substrate through the layer with a dose of .gtoreq. about 10.sup.15 ions/cm.sup.2 and a subsequence anneal at a temperature of .gtoreq. about 500.degree. C. for a predetermined time.

摘要翻译： 公开了覆盖基板的薄介电无机层，其厚度为约20nm，通过BV测量确定的缺陷密度为约0.6缺陷/ cm2。 还公开了一种形成这种层的方法，根据该方法，在基底上形成具有所需组成和厚度的层，然后通过层的离子注入到基底中，剂量为≥约1015个离子/ cm 2，并且在≥约500℃的温度下进行亚序列退火预定的时间。