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公开(公告)号：US11437510B2
公开(公告)日：2022-09-06
申请号：US17253597
申请日：2019-12-27
摘要： The present disclosure discloses a trench MOSFET and a method of manufacturing trench MOSFET. The trench MOSFET includes a substrate, an epitaxial layer, a plurality of trenches, and body region; the substrate has a first conductivity type; the epitaxial layer has the first conductivity type; the plurality of trenches are formed in the epitaxial layer, and at least two of the plurality of trenches are communicated with each other a gate structure is provided in the trench; the body region has a second conductivity type and has a second conductivity type and is disposed among the plurality of trenches.
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2.发明申请公开(公告)号：US20170236930A1
公开(公告)日：2017-08-17
申请号：US15323108
申请日：2014-12-31
发明人： Xiaoru Sun , Hongwei Zhou , Mengbo Ruan
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0865 , H01L29/1095 , H01L29/36 , H01L29/66712
摘要： The present invention provides a vertical double-diffused metal-oxide semiconductor field-effect transistor and a manufacturing method. The manufacturing method comprises: providing a substrate of a first conductive type; growing a first epitaxial layer of the first conductive type above the substrate; forming column regions of the first conductive type and column regions of a second conductive type spaced in a staggered manner above the first epitaxial layer; forming a third epitaxial layer of the first conductive type above the column regions of the first conductive type, and forming a well region of the second conductive type above the column regions of the second conductive type; forming a gate region on a surface of the third epitaxial layer; forming a source region of the first conductive type in the well region of the second conductive type; and forming a gate metal layer, a source metal layer, and a drain metal layer.
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公开(公告)号：US12046664B2
公开(公告)日：2024-07-23
申请号：US18286152
申请日：2022-05-20
发明人： Pengfei Jia , Qiang Rui , Wei Li
IPC分类号： H01L29/739 , H01L29/08 , H01L29/45 , H01L29/66
CPC分类号： H01L29/7396 , H01L29/0856 , H01L29/452 , H01L29/66333
摘要： A vertical semiconductor structure with an integrated sampling structure and a method for manufacturing the same; the vertical semiconductor structure includes a vertical-semiconductor-structure unit cell, a sampling unit cell, a control electrode, a first electrode, a second electrode, and a sampling electrode. The sampling electrode performs real-time sampling of a voltage difference between the first electrode and the second electrode; a PN junction is formed between a first/second P-type diffusion region and a second N-type base region, which forms a potential barrier blocking electron emission from the sampling electrode. Therefore, a voltage signal of the sampling electrode is input into a protection circuit, which detects whether the vertical-semiconductor-structure unit cell is desaturated when it determines that the unit cell is in the open state. Second, a sampling resistor is connected between the sampling electrode and the first electrode to ensure the stable operation of the sampling unit cell.
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公开(公告)号：US09391182B2
公开(公告)日：2016-07-12
申请号：US14363728
申请日：2012-12-03
发明人： Hongxiang Tang , Yongsheng Sun , Jianxin Ji , Weiqing Ma
IPC分类号： H01L29/739 , H01L29/66 , H01L29/08 , H01L21/02 , H01L29/10
CPC分类号： H01L29/7397 , H01L21/02499 , H01L21/02634 , H01L29/0821 , H01L29/0834 , H01L29/1095 , H01L29/66333 , H01L29/66348 , H01L29/7395
摘要： A Trench Insulated Gate Bipolar Transistor (IGBT) and a manufacture method thereof are provided by the present invention, which belongs to the field of IGBT technical field. The manufacture method includes following steps: (1) preparing a semiconductor substrate; (2) forming an epitaxial layer grow on a first side of the semiconductor substrate by epitaxial growth; (3) preparing and forming a gate and an emitter of the Trench Insulated Gate Bipolar Transistor on a second side of the semiconductor substrate; (4) thinning the epitaxial layer to form a collector region; (5) metalizing the collector region to form a collector. The cost of the manufacture method is low and the performance of the Trench IGBT formed by the manufacture method is good.
摘要翻译： 本发明提供了一种属于IGBT技术领域的沟槽绝缘栅双极晶体管（IGBT）及其制造方法。 制造方法包括以下步骤：（1）制备半导体衬底; （2）通过外延生长在所述半导体衬底的第一侧上形成外延层; （3）在半导体衬底的第二面上制备和形成沟槽绝缘栅双极晶体管的栅极和发射极; （4）使外延层变薄以形成集电极区域; （5）使集电体区域金属化以形成集电体。 制造方法的成本低，并且由制造方法形成的沟槽IGBT的性能良好。
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5.发明授权公开(公告)号：US09356213B2
公开(公告)日：2016-05-31
申请号：US14862978
申请日：2015-09-23
发明人： Lei Wang , Guoqi Li , Zhiyan Yu , Rongsheng Pu
CPC分类号： H01L33/62 , H01L33/0075 , H01L33/08 , H01L33/22 , H01L33/38 , H01L33/385 , H01L2933/0016 , H01L2933/0066
摘要： A manufacturing method of a light-emitting diode device. The light-emitting diode device comprises: a substrate (1); an epitaxial layer at one side of the substrate (1) and comprising an N-type layer (2), a P-type layer (4), and an active layer (3) between the N-type layer (2) and the P-type layer (4); an N-type electrode (5); a P-type electrode (7); an adhesive layer (8); and a patterned substrate (9). The light-emitting diode device further comprises an insulating layer (6) between the N-type electrode (5) and the P-type electrode (7), the insulating layer (6) electrically insulating the N-type electrode (5) and the P-type electrode (7). In the manufacturing method thereof, light-emitting efficiency and luminous efficiency of the light-emitting diode device can be improved, wiring is easier as compared with conventional chips, and the manufacturing process can be optimized.
摘要翻译： 一种发光二极管装置的制造方法。 所述发光二极管装置包括：基板（1）; 在衬底（1）的一侧上的外延层，包括N型层（2），P型层（4）和N型层（2）和 P型层（4）; N型电极（5）; P型电极（7）; 粘合层（8）; 和图案化衬底（9）。 所述发光二极管装置还包括在所述N型电极（5）和所述P型电极（7）之间的绝缘层（6），所述绝缘层（6）将所述N型电极（5）和 P型电极（7）。 在其制造方法中，可以提高发光二极管器件的发光效率和发光效率，与常规芯片相比，布线更容易，并且可以优化制造工艺。
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6.发明申请公开(公告)号：US20160013386A1
公开(公告)日：2016-01-14
申请号：US14862978
申请日：2015-09-23
发明人： Lei Wang , Guoqi Li , Zhiyan Yu , Rongsheng Pu
CPC分类号： H01L33/62 , H01L33/0075 , H01L33/08 , H01L33/22 , H01L33/38 , H01L33/385 , H01L2933/0016 , H01L2933/0066
摘要： A manufacturing method of a light-emitting diode device. The light-emitting diode device comprises: a substrate (1); an epitaxial layer at one side of the substrate (1) and comprising an N-type layer (2), a P-type layer (4), and an active layer (3) between the N-type layer (2) and the P-type layer (4); an N-type electrode (5); a P-type electrode (7); an adhesive layer (8); and a patterned substrate (9). The light-emitting diode device further comprises an insulating layer (6) between the N-type electrode (5) and the P-type electrode (7), the insulating layer (6) electrically insulating the N-type electrode (5) and the P-type electrode (7). In the manufacturing method thereof, light-emitting efficiency and luminous efficiency of the light-emitting diode device can be improved, wiring is easier as compared with conventional chips, and the manufacturing process can be optimized.
摘要翻译： 发光二极管装置的制造方法。 所述发光二极管装置包括：基板（1）; 在衬底（1）的一侧上的外延层，包括N型层（2），P型层（4）和N型层（2）和 P型层（4）; N型电极（5）; P型电极（7）; 粘合层（8）; 和图案化衬底（9）。 所述发光二极管装置还包括在所述N型电极（5）和所述P型电极（7）之间的绝缘层（6），所述绝缘层（6）将所述N型电极（5）和 P型电极（7）。 在其制造方法中，可以提高发光二极管器件的发光效率和发光效率，与常规芯片相比，布线更容易，并且可以优化制造工艺。
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7.发明授权Low-pressure chemical vapor deposition apparatus and thin-film deposition method thereof 有权低压化学气相沉积装置及其薄膜沉积方法公开(公告)号：US09478440B2
公开(公告)日：2016-10-25
申请号：US14363719
申请日：2012-12-03
发明人： Xunhui Wang , Xiao Wu , Qijun Guo , Jianchao Fan
IPC分类号： C23C16/455 , C23C16/448 , C23C16/453 , H01L21/3215
CPC分类号： H01L21/32155 , C23C16/448 , C23C16/453 , C23C16/455 , C23C16/45502
摘要： A low-pressure chemical vapor deposition (LPCVD) apparatus and a thin-film deposition method thereof. The apparatus comprises a reaction furnace, having reaction gas input pipelines respectively arranged at a furnace opening part and a furnace tail part. During thin film deposition, each reaction gas is synchronously introduced into the reaction furnace through the input pipeline at the furnace opening part and the input pipeline at the furnace tail part.
摘要翻译： 低压化学气相沉积（LPCVD）装置及其薄膜沉积方法。 该装置包括反应炉，其具有分别布置在炉开口部分和炉尾部分的反应气体输入管线。 在薄膜沉积期间，每个反应气体通过炉开口部分的输入管道和炉尾部分的输入管线同步引入反应炉。
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公开(公告)号：US20140367697A1
公开(公告)日：2014-12-18
申请号：US14376080
申请日：2012-12-03
发明人： Lei Wang , Guoqi Li , Zhiyan Yu , Rongsheng Pu
IPC分类号： H01L33/38
CPC分类号： H01L33/62 , H01L33/0075 , H01L33/08 , H01L33/22 , H01L33/38 , H01L33/385 , H01L2933/0016 , H01L2933/0066
摘要： A light-emitting diode device and a manufacturing method thereof. The light-emitting diode device comprises: a substrate (1); an epitaxial layer at one side of the substrate (1) and comprising an N-type layer (2), a P-type layer (4), and an active layer (3) between the N-type layer (2) and the P-type layer (4); an N-type electrode (5); a P-type electrode (7); an adhesive layer (8); and a patterned substrate (9). The light-emitting diode device further comprises an insulating layer (6) between the N-type electrode (5) and the P-type electrode (7), the insulating layer (6) electrically insulating the N-type electrode (5) and the P-type electrode (7). In the light-emitting diode device and the manufacturing method thereof, light-emitting efficiency and luminous efficiency of the light-emitting diode device can be improved, wiring is easier as compared with conventional chips, and the manufacturing process can be optimized.
摘要翻译： 发光二极管装置及其制造方法。 所述发光二极管装置包括：基板（1）; 在衬底（1）的一侧上的外延层，包括N型层（2），P型层（4）和N型层（2）和 P型层（4）; N型电极（5）; P型电极（7）; 粘合层（8）; 和图案化衬底（9）。 所述发光二极管装置还包括在所述N型电极（5）和所述P型电极（7）之间的绝缘层（6），所述绝缘层（6）将所述N型电极（5）和 P型电极（7）。 在发光二极管装置及其制造方法中，可以提高发光二极管装置的发光效率和发光效率，与常规芯片相比，布线更容易，并且可以优化制造工艺。
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9.发明申请LOW-PRESSURE CHEMICAL VAPOR DEPOSITION APPARATUS AND THIN-FILM DEPOSITION METHOD THEREOF 有权低压化学蒸气沉积装置及其薄膜沉积方法公开(公告)号：US20140322900A1
公开(公告)日：2014-10-30
申请号：US14363719
申请日：2012-12-03
发明人： Xunhui Wang , Xiao Wu , Qijun Guo , Jianchao Fan
IPC分类号： H01L21/3215 , C23C16/448 , C23C16/453
CPC分类号： H01L21/32155 , C23C16/448 , C23C16/453 , C23C16/455 , C23C16/45502
摘要： A low-pressure chemical vapor deposition (LPCVD) apparatus and a thin-film deposition method thereof The apparatus comprises a reaction furnace, having reaction gas input pipelines respectively arranged at a furnace opening part and a furnace tail part. During thin film deposition, each reaction gas is synchronously introduced into the reaction furnace through the input pipeline at the furnace opening part and the input pipeline at the furnace tail part.
摘要翻译： 一种低压化学气相沉积（LPCVD）装置及其薄膜沉积方法该装置包括反应炉，反应气体输入管线分别设置在炉开口部分和炉尾部分。 在薄膜沉积期间，每个反应气体通过炉开口部分的输入管道和炉尾部分的输入管线同步引入反应炉。
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10.发明公开公开(公告)号：US20240088273A1
公开(公告)日：2024-03-14
申请号：US18286152
申请日：2022-05-20
发明人： PENGFEI JIA , QIANG RUI , WEI LI
IPC分类号： H01L29/739 , H01L29/08 , H01L29/45 , H01L29/66
CPC分类号： H01L29/7396 , H01L29/0856 , H01L29/452 , H01L29/66333
摘要： A vertical semiconductor structure with an integrated sampling structure and a method for manufacturing the same; the vertical semiconductor structure includes a vertical-semiconductor-structure unit cell, a sampling unit cell, a control electrode, a first electrode, a second electrode, and a sampling electrode. The sampling electrode performs real-time sampling of a voltage difference between the first electrode and the second electrode; a PN junction is formed between a first/second P-type diffusion region and a second N-type base region, which forms a potential barrier blocking electron emission from the sampling electrode. Therefore, a voltage signal of the sampling electrode is input into a protection circuit, which detects whether the vertical-semiconductor-structure unit cell is desaturated when it determines that the unit cell is in the open state. Second, a sampling resistor is connected between the sampling electrode and the first electrode to ensure the stable operation of the sampling unit cell.
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