公开(公告)号：US09041058B2

公开(公告)日：2015-05-26

申请号：US13615799

申请日：2012-09-14

申请人： Yasushi Tateshita

发明人： Yasushi Tateshita

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836 ,  H01L29/7845

摘要： A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided.

摘要翻译： 一种制造晶体管的方法，其中可以在混合晶体层中的Ge和C的允许允许浓度范围内对沟道区域施加足够的应力。 还提供了半导体器件。

公开(公告)号：US20130009210A1

公开(公告)日：2013-01-10

申请号：US13615799

申请日：2012-09-14

申请人： Yasushi Tateshita

发明人： Yasushi Tateshita

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836 ,  H01L29/7845

摘要： A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided.

摘要翻译： 一种制造晶体管的方法，其中可以在混合晶体层中的Ge和C的允许允许浓度范围内对沟道区域施加足够的应力。 还提供了半导体器件。

公开(公告)号：US09070783B2

公开(公告)日：2015-06-30

申请号：US12530797

申请日：2008-02-27

申请人： Shinya Yamakawa ,  Yasushi Tateshita

发明人： Shinya Yamakawa ,  Yasushi Tateshita

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L27/0922 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： It is to enhance a current increasing effect by increasing a stress applied on a channel of a transistor. The invention is characterized by comprising: side wall insulating films 33 and 53 formed on a semiconductor substrate 11 with trenches 39 and 59 which are formed by removing dummy gates; gate electrodes 43 and 63 formed within the trenches 39 and 59 through a gate insulating film 41; first and second stress applying films 21 and 22 respectively formed along the side wall insulating films 33 and 53 over the semiconductor substrate 11; and source/drain regions 35, 36, 55, and 56 which are formed in the semiconductor substrate 11 on the both sides of the gate electrodes 43 and 63, in that the stress applying films 21 and 22 are formed before the first trench 39 and the second trench 59 are formed.

摘要翻译： 通过增加施加在晶体管的沟道上的应力来增强电流增加的效果。 本发明的特征在于包括：形成在具有通过去除伪栅极形成的沟槽39和59的半导体衬底11上的侧壁绝缘膜33和53; 通过栅极绝缘膜41形成在沟槽39和59内的栅电极43和63; 分别沿着半导体基板11上的侧壁绝缘膜33和53形成的第一和第二应力施加膜21和22; 以及形成在栅电极43和63的两侧上的半导体衬底11中的源极/漏极区域35,36,55和56，其中应力施加膜21和22形成在第一沟槽39和 形成第二沟槽59。

公开(公告)号：US20110269259A1

公开(公告)日：2011-11-03

申请号：US13178624

申请日：2011-07-08

申请人： Keiji Tatani ,  Takuji Matsumoto ,  Yasushi Tateshita ,  Fumihiko Koga ,  Takashi Nagano ,  Takahiro Toyoshima ,  Tetsuji Yamaguchi ,  Keiichi Nakazawa ,  Naoyuki Miyashita ,  Yoshihiko Nagahama

发明人： Keiji Tatani ,  Takuji Matsumoto ,  Yasushi Tateshita ,  Fumihiko Koga ,  Takashi Nagano ,  Takahiro Toyoshima ,  Tetsuji Yamaguchi ,  Keiichi Nakazawa ,  Naoyuki Miyashita ,  Yoshihiko Nagahama

IPC分类号： H01L31/02

CPC分类号： H01L27/1463 ,  H01L27/14609 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14689 ,  H01L27/14831

摘要： A solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.

摘要翻译： 一种固体摄像器件，包括像素部分，外围电路部分，在外围电路部分中的半导体衬底上形成有STI结构的第一隔离区域和在半导体衬底上形成有STI结构的第二隔离区域 在像素部分。 埋在半导体衬底中的第二隔离区的部分比第一隔离区的半导体衬底的部分浅，第二隔离区的上表面的高度等于第一隔离区的高度。 还公开了制造固态成像装置的方法和设置有固态成像装置的电子装置。

公开(公告)号：US20100001323A1

公开(公告)日：2010-01-07

申请号：US12518540

申请日：2007-12-07

申请人： Yasushi Tateshita

发明人： Yasushi Tateshita

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836 ,  H01L29/7845

摘要： Provided is a semiconductor device manufacturing method by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided. A dummy gate electrode 3 is formed on a Si substrate 1. Then, a recess region 7 is formed by recess etching by using the dummy gate electrode 3 as a mask. Next, on the surface of the recess region 7, a mixed crystal layer 8 composed of a SiGe layer is epitaxially grown. Subsequently, an interlayer insulating film 12 is formed on the mixed crystal layer 8 to cover the dummy gate electrode 3, and the interlayer insulating film 12 is removed until the surface of the dummy gate electrode 3 is exposed. A recess 13 is formed on the interlayer insulating film 12 to expose the Si substrate 1 by removing the dummy gate electrode 3. Then, a gate electrode 15 is formed in the recess 13 by having a gate insulating film 14 in between.

摘要翻译： 提供了一种半导体器件制造方法，其可以在混合晶体层中的Ge和C的允许浓度范围内对沟道区域施加足够的应力。 还提供了半导体器件。 在Si衬底1上形成虚拟栅电极3.然后，通过使用伪栅极电极3作为掩模，通过凹陷蚀刻形成凹陷区域7。 接着，在凹部7的表面上外延生长由SiGe层构成的混晶层8。 随后，在混合晶体层8上形成层间绝缘膜12以覆盖伪栅电极3，去除层间绝缘膜12直至伪栅电极3的表面露出。 在层间绝缘膜12上形成有凹部13，通过除去虚设栅电极3而使Si基板1露出。然后，通过在其间具有栅极绝缘膜14，在凹部13中形成栅电极15。

公开(公告)号：US20080277740A1

公开(公告)日：2008-11-13

申请号：US12115931

申请日：2008-05-06

申请人： Yasushi Tateshita

发明人： Yasushi Tateshita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28194 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

摘要： In the present invention, there is provided a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.

摘要翻译： 在本发明中，提供了一种半导体器件，包括：元件隔离区域，被形成为埋在半导体衬底中，使得半导体衬底的元件形成区域插入在元件隔离区域之间; 栅电极，形成在元件形成区上，栅极绝缘膜介于栅电极和元件形成区之间，栅电极形成为跨越元件形成区; 以及形成在栅电极两侧的元件形成区域中的源极 - 漏极区域，其中由栅极电极下方的元件形成区域形成的沟道区域形成为从元件隔离区域突出，并且源极 - 漏极 区域形成在比元件隔离区域的表面更深的位置。

公开(公告)号：US08728852B2

公开(公告)日：2014-05-20

申请号：US13178624

申请日：2011-07-08

申请人： Keiji Tatani ,  Takuji Matsumoto ,  Yasushi Tateshita ,  Fumihiko Koga ,  Takashi Nagano ,  Takahiro Toyoshima ,  Tetsuji Yamaguchi ,  Keiichi Nakazawa ,  Naoyuki Miyashita ,  Yoshihiko Nagahama

发明人： Keiji Tatani ,  Takuji Matsumoto ,  Yasushi Tateshita ,  Fumihiko Koga ,  Takashi Nagano ,  Takahiro Toyoshima ,  Tetsuji Yamaguchi ,  Keiichi Nakazawa ,  Naoyuki Miyashita ,  Yoshihiko Nagahama

IPC分类号： H01L31/02

CPC分类号： H01L27/1463 ,  H01L27/14609 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14689 ,  H01L27/14831

摘要： A solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.

摘要翻译： 一种固体摄像器件，包括像素部分，外围电路部分，在外围电路部分中的半导体衬底上形成有STI结构的第一隔离区域和在半导体衬底上形成有STI结构的第二隔离区域 在像素部分。 埋在半导体衬底中的第二隔离区的部分比第一隔离区的半导体衬底的部分浅，第二隔离区的上表面的高度等于第一隔离区的高度。 还公开了制造固态成像装置的方法和设置有固态成像装置的电子装置。

公开(公告)号：US08354631B2

公开(公告)日：2013-01-15

申请号：US12656423

申请日：2010-01-29

申请人： Yasushi Tateshita

发明人： Yasushi Tateshita

IPC分类号： H01L31/00 ,  H01L21/70

CPC分类号： H01L31/0216 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/14603 ,  H01L27/14683

摘要： A solid-state image device is provided which includes: a photoelectric conversion portion which obtains a signal charge by photoelectric conversion of incident light; a pixel transistor portion which outputs a signal charge generated by the photoelectric conversion portion; a peripheral circuit portion which is provided at the periphery of a pixel portion including the photoelectric conversion portion and the pixel transistor portion and which has an NMOS transistor and a PMOS transistor; a first stress liner film which has a compressive stress and which is provided on the PMOS transistor; and a second stress liner film which has a tensile stress and which is provided on the NMOS transistor. In the solid-state image device described above, the photoelectric conversion portion, the pixel transistor portion, and the peripheral circuit portion are provided in and/or on a semiconductor substrate.

摘要翻译： 提供一种固态图像装置，其包括：光电转换部，其通过入射光的光电转换获得信号电荷; 输出由光电转换部生成的信号电荷的像素晶体管部; 外围电路部分设置在包括光电转换部分和像素晶体管部分的像素部分的周围，并且具有NMOS晶体管和PMOS晶体管; 第一应力衬垫膜，其具有压应力并且设置在PMOS晶体管上; 以及具有拉伸应力并设置在NMOS晶体管上的第二应力衬垫膜。 在上述固体摄像装置中，将光电转换部，像素晶体管部和外围电路部设置在半导体基板的和/或半导体基板上。

公开(公告)号：US08298011B2

公开(公告)日：2012-10-30

申请号：US13080794

申请日：2011-04-06

申请人： Yasushi Tateshita

发明人： Yasushi Tateshita

IPC分类号： H01L21/3205

CPC分类号： H01L29/7846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28194 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

摘要： A method for making a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.

摘要翻译： 一种制造半导体器件的方法，包括：以掩模在半导体衬底中的状态形成的元件隔离区域，使得半导体衬底的元件形成区域插入在元件隔离区域之间; 栅电极，形成在元件形成区上，栅极绝缘膜介于栅电极和元件形成区之间，栅电极形成为跨越元件形成区; 以及形成在栅电极两侧的元件形成区域中的源极 - 漏极区域，其中由栅极电极下方的元件形成区域形成的沟道区域形成为从元件隔离区域突出，并且源极 - 漏极 区域形成在比元件隔离区域的表面更深的位置。

公开(公告)号：US20100026866A1

公开(公告)日：2010-02-04

申请号：US12509995

申请日：2009-07-27

申请人： Takuji Matsumoto ,  Keiji Tatani ,  Yasushi Tateshita ,  Kazuichiro Itonaga

发明人： Takuji Matsumoto ,  Keiji Tatani ,  Yasushi Tateshita ,  Kazuichiro Itonaga

IPC分类号： H04N5/335 ,  H01L31/18

CPC分类号： H01L27/14614 ,  H01L27/14605 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14689 ,  H01L29/51 ,  H01L29/518 ,  H04N5/335 ,  H04N5/378

摘要： A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of a MOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of a MOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.

摘要翻译： 固态成像装置在半导体衬底中包括设置有光电转换部分的像素部分，其对入射光进行光电转换以获得电信号，并且设置在像素部分周围的外围电路部分，其中栅极 外围电路部的MOS晶体管的绝缘膜由氮氧化硅膜构成，像素部中的MOS晶体管的栅极绝缘膜由氮氧化硅膜构成，氧化膜位于光电转换的正上方 像素部分中的部分。