公开(公告)号：US07679202B2

公开(公告)日：2010-03-16

申请号：US11790123

申请日：2007-04-24

Applicant: Shigeki Yoshida ,  Fumio Ushida ,  Nobuhisa Naori ,  Yasutaka Ozaki

Inventor： Shigeki Yoshida ,  Fumio Ushida ,  Nobuhisa Naori ,  Yasutaka Ozaki

IPC: H01L23/544 ,  H01L21/304 ,  H01L21/76

CPC classification number: H01L23/544 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.

Abstract translation: 构成电子电路的一部分的多个器件图案形成在衬底的表面上。 用于识别符号的符号图案形成在与设备图案相同的层中。 设备图案的宽度在设计规则的图案宽度范围内。 符号图案由多个隔离元件图案形成。 元素图案是线性图案或点图案。 元件图案的宽度等于或大于图案宽度范围的下限值的0.8倍，并且等于或小于图案宽度范围的上限值的1.2倍。

公开(公告)号：US07297558B2

公开(公告)日：2007-11-20

申请号：US11106580

申请日：2005-04-15

Applicant: Yasutaka Ozaki ,  Tatsuya Yokota ,  Nobutaka Ohyagi

Inventor： Yasutaka Ozaki ,  Tatsuya Yokota ,  Nobutaka Ohyagi

IPC: H01L21/00

CPC classification number: H01L27/11502 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/3144 ,  H01L21/76829 ,  H01L21/76834 ,  H01L27/11507

Abstract: A W plug (24) is formed and a W oxidation preventing barrier metal film (25) is formed thereon. After that, an SiON film (27) thinner than the W oxidation preventing barrier metal film (25) is formed and Ar sputter etching is performed on the SiON film (27). As a result, the shape of the surface of the SiON film (27) becomes gentler and deep trenches disappear. Next, an SiON film (28) is formed on the whole surface. A voidless W oxidation preventing insulating film (29) is composed of the SiON (28) film and the SiON film (27).

Abstract translation: 形成W插头（24），并在其上形成W氧化防止阻挡金属膜（25）。 之后，形成比W氧化防止阻挡金属膜（25）薄的SiON膜（27），对SiON膜（27）进行Ar溅射蚀刻。 结果，SiON膜（27）的表面的形状变得较平缓，深的沟槽消失。 接下来，在整个表面上形成SiON膜（28）。 无孔W氧化防止绝缘膜（29）由SiON（28）膜和SiON膜（27）构成。

公开(公告)号：US06913970B2

公开(公告)日：2005-07-05

申请号：US10303752

申请日：2002-11-26

Applicant: Kenichi Inoue ,  Yoshinori Obata ,  Takeyasu Saito ,  Kaoru Saigoh ,  Naoya Sashida ,  Koji Tani ,  Jirou Miura ,  Tatsuya Yokota ,  Satoru Mihara ,  Yukinobu Hikosaka ,  Yasutaka Ozaki

Inventor： Kenichi Inoue ,  Yoshinori Obata ,  Takeyasu Saito ,  Kaoru Saigoh ,  Naoya Sashida ,  Koji Tani ,  Jirou Miura ,  Tatsuya Yokota ,  Satoru Mihara ,  Yukinobu Hikosaka ,  Yasutaka Ozaki

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/20

CPC classification number: H01L27/11502 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L27/11507 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

Abstract translation: 通过在绝缘膜上形成接触孔而形成的半导体器件，其通过相同的步骤在电容器的下电极上覆盖MOSFET的源/漏和存储单元区域中的电容器，然后将插头填充到接触孔 ，然后在电容器的上电极上形成接触孔。 因此，可以提供具有铁电电容器的半导体器件，其能够通过抑制在晶体管上形成的电容器的损坏来简化与电容器的上部电极和下部电极的各个布线连接结构。

公开(公告)号：US08125014B2

公开(公告)日：2012-02-28

申请号：US11293893

申请日：2005-12-05

Applicant: Yasutaka Ozaki

Inventor： Yasutaka Ozaki

IPC: H01L29/76

CPC classification number: H01L21/76879 ,  H01L21/76816 ,  H01L21/76829 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/65

Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm.

Abstract translation: 开口通过光刻和随后的干蚀刻形成在第一保护膜的对应于稍后将描述的第二插塞的连接孔的部分处，即在与第一插塞对准的部分处，其中开口的直径大于 连接孔约0.4μm。

公开(公告)号：US07598557B2

公开(公告)日：2009-10-06

申请号：US11051643

申请日：2005-01-27

Applicant: Kouichi Nagai ,  Hideaki Kikuchi ,  Naoya Sashida ,  Yasutaka Ozaki

Inventor： Kouichi Nagai ,  Hideaki Kikuchi ,  Naoya Sashida ,  Yasutaka Ozaki

IPC: H01L27/108

CPC classification number: H01L27/11502 ,  H01L21/02063 ,  H01L27/0688 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/57

Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected to the second conductor plug 62 or the third conductor plug 62.

Abstract translation: 半导体器件包括形成在半导体衬底10上的第一绝缘膜26，埋在第一接触孔28a中的第一导体插塞32，第一接触孔28a形成在源极/漏极扩散层22上，形成在第一绝缘膜26上的电容器44 在第一绝缘膜26上形成的覆盖电容器44的第一氢扩散防止膜48，形成在第一氢扩散防止膜上并具有表面平坦化的第二绝缘膜50，形成在第一氢上的第二氢扩散防止膜52 具有表面平坦化的扩散防止膜26，形成在第二绝缘膜50上的第二氢扩散防止膜52，埋在第二接触孔56中的第二导体插塞62，第二接触孔56形成在下电极38或下电极38的上电极42 电容器44，埋在第一接触孔58中的第三导体插头62，并形成在第一导体插塞32的下方 连接到第二导体插头62或第三导体插头62的部分64。

公开(公告)号：US20070296091A1

公开(公告)日：2007-12-27

申请号：US11790123

申请日：2007-04-24

Applicant: Shigeki Yoshida ,  Fumio Ushida ,  Nobuhisa Naori ,  Yasutaka Ozaki

Inventor： Shigeki Yoshida ,  Fumio Ushida ,  Nobuhisa Naori ,  Yasutaka Ozaki

IPC: H01L23/544 ,  H01L21/304

CPC classification number: H01L23/544 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.

Abstract translation: 构成电子电路的一部分的多个器件图案形成在衬底的表面上。 用于识别符号的符号图案形成在与设备图案相同的层中。 设备图案的宽度在设计规则的图案宽度范围内。 符号图案由多个隔离元件图案形成。 元素图案是线性图案或点图案。 元件图案的宽度等于或大于图案宽度范围的下限值的0.8倍，并且等于或小于图案宽度范围的上限值的1.2倍。

公开(公告)号：US06570203B2

公开(公告)日：2003-05-27

申请号：US09819738

申请日：2001-03-29

Applicant: Yukinobu Hikosaka ,  Yasutaka Ozaki ,  Kazuaki Takai

Inventor： Yukinobu Hikosaka ,  Yasutaka Ozaki ,  Kazuaki Takai

IPC: H01L31119

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10894 ,  H01L27/11507 ,  H01L28/55

Abstract: There is provided a semiconductor device which comprises a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.

公开(公告)号：US07462898B2

公开(公告)日：2008-12-09

申请号：US11296459

申请日：2005-12-08

Applicant: Yasutaka Ozaki

Inventor： Yasutaka Ozaki

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/65

Abstract: A ferroelectric capacitor is formed above a substrate and made of a lamination of a lower electrode, a capacitor ferroelectric film and an upper electrode stacked in this order. The upper electrode is made of conductive oxide and has such an oxygen concentration distribution as an oxygen concentration in a lower layer region of the upper electrode becomes lower than an oxygen concentration in an upper layer region. An interlayer insulating film covers the ferroelectric capacitor. A via hole is formed through the interlayer insulating film and reaches a position deeper than an upper surface of the upper electrode. The via hole is stopped at a position shallower than a position at which the oxygen concentration of the upper electrode becomes maximum. A conductive member contacts the upper electrode on a bottom of the via hole.

Abstract translation: 在基板的上方形成铁电电容器，并且由下电极，电容器铁电体膜和上电极的叠层构成。 上部电极由导电氧化物形成，并且具有如上氧电极的下层区域中的氧浓度的氧浓度分布变得低于上层区域中的氧浓度。 层间绝缘膜覆盖铁电电容器。 通过层间绝缘膜形成通孔，并且到达比上电极的上表面更深的位置。 通孔停止在比上电极的氧浓度变得最大的位置浅​​的位置。 导电构件在通孔的底部接触上电极。

公开(公告)号：US20060273368A1

公开(公告)日：2006-12-07

申请号：US11296459

申请日：2005-12-08

Applicant: Yasutaka Ozaki

Inventor： Yasutaka Ozaki

IPC: H01L29/94

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/65

Abstract: A ferroelectric capacitor is formed above a substrate and made of a lamination of a lower electrode, a capacitor ferroelectric film and an upper electrode stacked in this order. The upper electrode is made of conductive oxide and has such an oxygen concentration distribution as an oxygen concentration in a lower layer region of the upper electrode becomes lower than an oxygen concentration in an upper layer region. An interlayer insulating film covers the ferroelectric capacitor. A via hole is formed through the interlayer insulating film and reaches a position deeper than an upper surface of the upper electrode. The via hole is stopped at a position shallower than a position at which the oxygen concentration of the upper electrode becomes maximum. A conductive member contacts the upper electrode on a bottom of the via hole.

Abstract translation: 在基板的上方形成铁电电容器，并且由下电极，电容器铁电体膜和上电极的叠层构成。 上部电极由导电氧化物形成，并且具有如上氧电极的下层区域中的氧浓度的氧浓度分布变得低于上层区域中的氧浓度。 层间绝缘膜覆盖铁电电容器。 通过层间绝缘膜形成通孔，并且到达比上电极的上表面更深的位置。 通孔停止在比上电极的氧浓度变得最大的位置浅​​的位置。 导电构件在通孔的底部接触上电极。

公开(公告)号：US20060118957A1

公开(公告)日：2006-06-08

申请号：US11093242

申请日：2005-03-30

Applicant: Yasutaka Ozaki

Inventor： Yasutaka Ozaki

IPC: H01L23/52

CPC classification number: H01L27/11507 ,  H01L21/76816 ,  H01L21/76832 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/65

Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm.

Abstract translation: 开口通过光刻和随后的干蚀刻形成在第一保护膜的对应于稍后将描述的第二插塞的连接孔的部分处，即在与第一插塞对准的部分处，其中开口的直径大于 连接孔约0.4毫米。