公开(公告)号：US20140069271A1

公开(公告)日：2014-03-13

申请号：US14117637

申请日：2012-05-21

Applicant: Koichiro Ishibashi ,  Koji Hara ,  Toshio Sato

Inventor： Koichiro Ishibashi ,  Koji Hara ,  Toshio Sato

IPC: F16J1/12

CPC classification number: F16J1/12 ,  F15B15/1447 ,  F16J1/008 ,  Y10T29/49826

Abstract: A coupling structure for a piston used in a fluid-pressure cylinder. The piston in the fluid-pressure cylinder includes a piston hole that runs through a central part of the piston in an axial direction thereof. One end of a piston rod and a coupling body coupled to the one end are inserted into the piston hole. The coupling body includes: a main part that contacts the one end of the piston rod; and an angled part formed around the main part and inclined at a prescribed angle with respect thereto. When the coupling body is subjected to pressure inside the piston hole, the diameter of the coupling body increases and a pointed edge of the angled part engages with an inner surface of the piston hole such that the coupling body couples the piston and the piston rod.

Abstract translation: 用于流体压力缸中的活塞的联接结构。 流体压缸中的活塞包括活塞孔，该活塞孔沿着活塞的轴向延伸穿过活塞的中心部分。 活塞杆的一端和联接在一端的联接体插入活塞孔。 联接体包括：与活塞杆的一端接触的主要部分; 以及围绕主要部分形成并相对于其倾斜一定角度的倾斜部分。 当联接体在活塞孔内部受到压力时，联接体的直径增加，并且成角度部分的尖端与活塞孔的内表面接合，使得联接体联接活塞和活塞杆。

公开(公告)号：US20110273952A1

公开(公告)日：2011-11-10

申请号：US13186769

申请日：2011-07-20

Applicant: Koji NII ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

Inventor： Koji NII ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

IPC: G11C5/14

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20110208983A1

公开(公告)日：2011-08-25

申请号：US13101678

申请日：2011-05-05

Applicant: Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

Inventor： Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

IPC: G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract translation: 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US07737509B2

公开(公告)日：2010-06-15

申请号：US12216716

申请日：2008-07-10

Applicant: Koichiro Ishibashi ,  Kenichi Osada

Inventor： Koichiro Ishibashi ,  Kenichi Osada

IPC: H01L27/088

CPC classification number: G11C11/404 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/104 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract translation: 在集成电路器件中，根据电路的特性，存在各种最佳栅极长度，栅极氧化物膜的厚度和阈值电压。 在其中电路集成在同一基板上的半导体集成电路器件中，制造过程复杂以便将电路设置为最佳值。 结果，伴随着产量的恶化和制造日数的增加，制造成本增加。 为了解决这些问题，根据本发明，在逻辑电路中使用高阈值和低阈值的晶体管，存储单元使用具有相同高阈值电压的晶体管和低阈值电压晶体管，以及输入/输出电路 使用在通道中具有相同高阈值电压和相同浓度的晶体管，以及较厚的栅极氧化物膜。

公开(公告)号：US20090269899A1

公开(公告)日：2009-10-29

申请号：US12457917

申请日：2009-06-25

Applicant: Kenichi OSADA ,  Koichiro ISHIBASHI ,  Yoshikazu SAITOH ,  Akio NISHIDA ,  Masaru NAKAMICHI ,  Naoki KITAI

Inventor： Kenichi OSADA ,  Koichiro ISHIBASHI ,  Yoshikazu SAITOH ,  Akio NISHIDA ,  Masaru NAKAMICHI ,  Naoki KITAI

IPC: H01L21/8244

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US07397282B2

公开(公告)日：2008-07-08

申请号：US11526612

申请日：2006-09-26

Applicant: Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Masayuki Miyazaki

Inventor： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Masayuki Miyazaki

IPC: H03K3/01

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H03K3/011 ,  H03K3/0315 ,  H03K19/0016

Abstract: A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.

Abstract translation: 一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及 缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入 所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。

公开(公告)号：US20070215952A1

公开(公告)日：2007-09-20

申请号：US11614619

申请日：2006-12-21

Applicant: Osamu OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

Inventor： Osamu OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

IPC: H01L29/76

CPC classification number: H01L27/1203 ,  H01L21/823857

Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

Abstract translation: 半导体集成电路具有所谓的SOI型第一MOS晶体管（MNtk，MPtk）和第二MOS晶体管（MNtn，MPtn）。 第一MOS晶体管具有比第二MOS晶体管更厚的栅极隔离膜。 第一和第二MOS晶体管构成电源可中断电路（6）和电源不间断电路（7）。 电源中断电路具有构成源极线（VDD）和接地线（VSS）之间的电源开关（10）的第一MOS晶体管，以及与电源开关串联连接的第二MOS晶体管。 构成功率开关的第一MOS晶体管的栅极控制信号的幅度比第二MOS晶体管的幅度大。 这使得能够实现与SOI原理的SOI型半导体集成电路的器件隔离结构相当的高度灵活性的电源切断控制。

公开(公告)号：US07251183B2

公开(公告)日：2007-07-31

申请号：US11148354

申请日：2005-06-09

Applicant: Kiyoo Itoh ,  Koichiro Ishibashi

Inventor： Kiyoo Itoh ,  Koichiro Ishibashi

IPC: G11C11/412

CPC classification number: H01L27/105 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/1104 ,  H01L27/1116 ,  Y10S257/903

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract translation: 由具有相对高阈值电压的交叉耦合MOS晶体管组成的静态存储单元配备有用于控制存储单元的电源线电压的MOS晶体管。 为了在从数据线对DL和/ DL向激活的存储单元中的两个节点施加写入数据时，允许非激活存储单元中的两个数据存储节点之间的电压差超过两个节点之间的电压差， 电源线电压控制晶体管导通，在字线电压关闭后，向电源线施加高电压VCH。 存储单元中的数据保持电压可以独立于数据线电压而被激活到高电压，并且可以动态地设置数据保持电压，使得能够以低功耗高速执行读和写操作。

公开(公告)号：US20070133260A1

公开(公告)日：2007-06-14

申请号：US11657026

申请日：2007-01-24

Applicant: Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

Inventor： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

IPC: G11C11/00

CPC classification number: G11C11/417 ,  G11C11/412 ,  Y10S257/903

Abstract: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

Abstract translation: 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

公开(公告)号：US07151395B2

公开(公告)日：2006-12-19

申请号：US11154061

申请日：2005-06-15

Applicant: Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

Inventor： Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

IPC: H03K3/356 ,  H03K3/286

CPC classification number: H03K3/0375 ,  H03K3/356156 ,  H03K3/3565 ,  H03K17/162 ,  H03K17/165 ,  H03K19/00338

Abstract: A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be put out, it is corrected by a pull-up path or a pull-down path, and when a soft error occurs in the data in the pull-up path or the pull-down path, the error data in the pull-up path or the pull-down path is prevented from affecting each other, as well as turning off the correcting function to prevent the influence on the data to be put out.