公开(公告)号：US20100194433A1

公开(公告)日：2010-08-05

申请号：US12759252

申请日：2010-04-13

申请人： Yong-Hwan NOH ,  Chul-Sung PARK

发明人： Yong-Hwan NOH ,  Chul-Sung PARK

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

摘要翻译： 提供了一种电平转换器和具有使用其的片外驱动器（OCD）的半导体器件。 电平移位器包括多个串联连接的逻辑门，其接收具有第一电源电压电平的第一状态输入信号，并产生具有第二电源电压电平的电平移位的第一状态输出信号。 逻辑门作为电源电压接收至少一个中间电源电压，其具有在第一电源电压电平和第二电源电压电平之间的中间的至少一个电压电平，并且施加到本逻辑门的中间电源电压为 等于或高于施加到先前逻辑门的中间电源电压。

公开(公告)号：US20080150615A1

公开(公告)日：2008-06-26

申请号：US11878498

申请日：2007-07-25

申请人： Yong-hwan Noh

发明人： Yong-hwan Noh

IPC分类号： G01R1/28

CPC分类号： G01R31/3004 ,  G01R1/28

摘要： A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.

摘要翻译： 用于提供参考电压的系统包括适于提供预定电流的测试器，连接到测试仪的接地电压的第一接地焊盘，连接在测试器和第一接地焊盘之间的第二接地焊盘，第二接地焊盘被连接 通过第一和第二电阻器连接到测试器，参考电压焊盘连接到第一和第二电阻器之间的节点，适用于提供测试参考电压的参考电压焊盘以及连接到参考电压焊盘的多路复用器，多路复用器被配置为 在基本电压变化期间输出测试参考电压作为参考电压。

公开(公告)号：US07151710B2

公开(公告)日：2006-12-19

申请号：US11123996

申请日：2005-05-06

申请人： Hyang Ja Yang ,  Yong Hwan Noh ,  Yun Jin Cho ,  Chul Sung Park

发明人： Hyang Ja Yang ,  Yong Hwan Noh ,  Yun Jin Cho ,  Chul Sung Park

IPC分类号： G11C8/00

CPC分类号： G11C7/1012 ,  G11C7/06 ,  G11C7/1045 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4097

摘要： The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.

摘要翻译： 本发明涉及半导体存储器件中的数据输入/输出组织系统和方法。 存储器件具有多个存储器阵列，在一个实施例中，存储器阵列的奇数个。 阵列被划分成块，并且块被分成段。 控制电路向存储器阵列提供控制信号，使得数据以9位的倍数输入和/或输出到存储器件。 数据位同时输入或输出，无需复用电路。 这导致功耗降低和内存处理速度提高。

公开(公告)号：US20050201184A1

公开(公告)日：2005-09-15

申请号：US11123996

申请日：2005-05-06

申请人： Hyang Yang ,  Yong Hwan Noh ,  Yun Cho ,  Chul Park

发明人： Hyang Yang ,  Yong Hwan Noh ,  Yun Cho ,  Chul Park

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/413 ,  G11C8/00

CPC分类号： G11C7/1012 ,  G11C7/06 ,  G11C7/1045 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4097

摘要： The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.

公开(公告)号：US06674686B2

公开(公告)日：2004-01-06

申请号：US10037906

申请日：2001-11-09

申请人： Yong-Hwan Noh ,  Young-Ho Suh

发明人： Yong-Hwan Noh ,  Young-Ho Suh

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C2207/107

摘要： Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. Read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time or read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4), wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time. In another aspect, when a read command is input in one cycle, a read operation is performed in synchronization with a rising edge of clock and a write operation is performed in synchronization with a signal that operates during the read operation.

摘要翻译： 在包括独立数据输入总线和数据输出总线的I / O（输入/输出）架构的半导体存储器件中执行读和写操作的方法和装置。 使用QDR2（四倍数据速率2）在相同周期中顺序地执行读写操作，其中每个输入和输出模式以2位突发模式和双倍数据速率（DDR）模式操作，从而最小化周期时间或 使用QDR4（四倍数据速率4）在相同周期中顺序地执行读和写操作，其中每个输入和输出模式以4位突发模式和DDR模式操作，从而最小化循环时间。 在另一方面，当在一个周期中输入读取命令时，与时钟的上升沿同步地执行读取操作，并且与在读取操作期间操作的信号同步地执行写入操作。

公开(公告)号：US06269050B1

公开(公告)日：2001-07-31

申请号：US09594888

申请日：2000-06-14

申请人： Kook-Hwan Kwon ,  Yong-Hwan Noh

发明人： Kook-Hwan Kwon ,  Yong-Hwan Noh

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22

摘要： An internal clock generating circuit of a synchronous type semiconductor memory device includes a transmission part for transmitting a first clock enable signal in response to applying a first level of a first clock signal. It also includes a latch part for latching the first clock enable signal transmitted from the transmission part. A gating part gates the latched first clock enable signal with the first clock signal to generate a second clock signal as an internal clock signal for the memory device. This reduces a time lag by which the speed of the internal clock is synchronized with the external clock signal.

摘要翻译： 同步型半导体存储器件的内部时钟发生电路包括用于响应于施加第一电平的第一时钟信号而发送第一时钟使能信号的发送部分。 它还包括用于锁存从发送部分发送的第一时钟使能信号的锁存部分。 门控部分利用第一时钟信号对锁存的第一时钟使能信号进行门控，以产生作为存储器件的内部时钟信号的第二时钟信号。 这减少了内部时钟的速度与外部时钟信号同步的时滞。

公开(公告)号：US06949960B2

公开(公告)日：2005-09-27

申请号：US10635253

申请日：2003-08-06

申请人： Chul-Sung Park ,  Hyang-Ja Yang ,  Hong-Kyun Kim ,  Yong-Hwan Noh

发明人： Chul-Sung Park ,  Hyang-Ja Yang ,  Hong-Kyun Kim ,  Yong-Hwan Noh

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R23/02

CPC分类号： G01R31/3172 ,  G01R31/31701

摘要： An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further includes registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.

摘要翻译： 集成电路器件包括用于接收直流电压分量信号的引脚。 该装置包括用于向引脚施加AC信号的信号源，用于将AC信号转换为数字信号的缓冲器，以及用于检测数字信号频率并输出预定检测信号的数字检测器。 当数字信号的频率大于或等于预定频率时，预定的检测信号被激活。 预定检测信号用作设定预定功能模式的信号。 该装置还包括用于产生多个功能模式信号的寄存器或差分放大器和解码器。

公开(公告)号：US20050056834A1

公开(公告)日：2005-03-17

申请号：US10976491

申请日：2004-10-30

申请人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

发明人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L22/34 ,  G01R31/2884

摘要： Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

摘要翻译： 公开了一种半导体集成电路器件，其包括连接在第一和第二焊盘之间的测试元件组电路。 测试元件组电路包括串联连接在第一和第二焊盘之间的多个半导体器件。 至少两个相邻的半导体器件通过由多层互连结构形成的信号路径相互连接。

公开(公告)号：US08030958B2

公开(公告)日：2011-10-04

申请号：US11878498

申请日：2007-07-25

申请人： Yong-hwan Noh

发明人： Yong-hwan Noh

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G01R1/28

摘要： A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.

摘要翻译： 用于提供参考电压的系统包括适于提供预定电流的测试器，连接到测试仪的接地电压的第一接地焊盘，连接在测试器和第一接地焊盘之间的第二接地焊盘，第二接地焊盘被连接 通过第一和第二电阻器连接到测试器，参考电压焊盘连接到第一和第二电阻器之间的节点，适用于提供测试参考电压的参考电压焊盘以及连接到参考电压焊盘的多路复用器，多路复用器被配置为 在基本电压变化期间输出测试参考电压作为参考电压。

公开(公告)号：US07801052B2

公开(公告)日：2010-09-21

申请号：US11905260

申请日：2007-09-28

申请人： Yong-hwan Noh

发明人： Yong-hwan Noh

IPC分类号： G01R31/08

CPC分类号： H04L12/66

摘要： A transmission delay measuring circuit may include a first transmission path, a second transmission path, an inversion circuit, a first multiplexer, and an output terminal. The second transmission path may have the same structure as the structure of the first transmission path and may receive the output of the first transmission path. The inversion circuit may invert the output of the second transmission path. The first multiplexer may output one of the external input signal and an inverted output of the second transmission path to the first transmission path in response to a test mode enable signal. The output terminal may output, as a measuring signal, a signal in an arbitrary node of a closed loop formed of the first transmission path, the second transmission path, the inversion circuit, and the first multiplexer. The transmission delay measuring apparatus may more accurately measure the transmission delay of a transmission path in a semiconductor device in a die-to-die wafer state or a package state.

摘要翻译： 传输延迟测量电路可以包括第一传输路径，第二传输路径，反转电路，第一多路复用器和输出端。 第二传输路径可以具有与第一传输路径的结构相同的结构，并且可以接收第一传输路径的输出。 反相电路可以反转第二传输路径的输出。 响应于测试模式使能信号，第一多路复用器可将外部输入信号和第二传输路径的反相输出中的一个输出到第一传输路径。 输出端子可以作为测量信号输出由第一传输路径，第二传输路径，反相电路和第一多路复用器形成的闭环的任意节点中的信号。 传输延迟测量装置可以更精确地测量半导体器件在晶片到芯片晶片状态或封装状态下的传输路径的传输延迟。