公开(公告)号：US20110280086A1

公开(公告)日：2011-11-17

申请号：US13105970

申请日：2011-05-12

申请人： Jang-seok CHOI ,  Yong-hoon KANG

发明人： Jang-seok CHOI ,  Yong-hoon KANG

IPC分类号： G11C7/00

CPC分类号： G11C7/24 ,  G11C7/1048 ,  G11C7/1078

摘要： A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells, and a filling command determiner that receives a command signal and an address signal and determines whether the command signal corresponds to a filling command. Upon determining that the command signal corresponds to a filling command, the filling command determiner connects a first source voltage to a bitline and connects a second source voltage to a complementary bitline corresponding to the bitline. The bitline is connected to a selected memory cell corresponding to the address signal.

摘要翻译： 半导体存储器件包括一个包括多个存储器单元的存储单元阵列，以及一个接收命令信号和地址信号并确定命令信号是否对应于填充命令的填充命令确定器。 当确定命令信号对应于填充命令时，填充命令确定器将第一源电压连接到位线，并将第二源电压连接到与位线相对应的补充位线。 位线连接到与地址信号对应的选定存储单元。

公开(公告)号：US20110235403A1

公开(公告)日：2011-09-29

申请号：US13053337

申请日：2011-03-22

申请人： Yong-hoon KANG

发明人： Yong-hoon KANG

IPC分类号： G11C29/04

CPC分类号： G11C29/04 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2029/1204

摘要： A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell. A detection reference point is changed upon wear indication to detect the resistance of the resistive memory cell. The resistance of the resistive memory cell is detected using the changed detection reference point to determine whether or not the resistive memory cell is worn by comparing the detected resistance to a wear reference level.

摘要翻译： 提出了一种用于管理磨损的电阻式存储器单元的方法和装置。 根据电阻式存储单元的磨损状态，使用正常的读取模式或磨损的存储单元检测模式。 在磨损指示上改变检测参考点以检测电阻式存储单元的电阻。 使用改变的检测参考点来检测电阻性存储单元的电阻，以通过将检测到的电阻与磨损参考电平进行比较来确定电阻性存储单元是否被磨损。

公开(公告)号：US20110122685A1

公开(公告)日：2011-05-26

申请号：US12905311

申请日：2010-10-15

申请人： Yong Hoon KANG ,  Dong Yang LEE

发明人： Yong Hoon KANG ,  Dong Yang LEE

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages.

摘要翻译： 多级单元（MLC）相变存储器件将数据划分成包括多位数据的数据组，并将每个数据组存储在所选择的相变存储单元中。 通过用对应于数据组的数据值的脉冲电流特性向所选择的相变存储单元施加脉冲电流，将数据组存储在选定的相变存储单元中。 脉冲电流特性可以包括例如脉冲电流的幅度，向下斜率或持续时间。 通过感测连接到所选择的相变存储器单元的位线的电压并将所感测的电压同时与多个参考电压进行比较，从所选择的相变存储器单元读取数据。

公开(公告)号：US20110063903A1

公开(公告)日：2011-03-17

申请号：US12832200

申请日：2010-07-08

申请人： Yong Hoon Kang ,  Dongyang Lee

发明人： Yong Hoon Kang ,  Dongyang Lee

IPC分类号： G11C11/00 ,  G06F12/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0038 ,  G11C2013/0078 ,  G11C2213/72

摘要： Provided is a nonvolatile memory device, a memory system having the same, and a write current control method thereof. The memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device has a plurality of write modes. The memory controller includes a sensor configured to sense environment information of the memory system. The memory controller is configured to select one of the write modes according to the sensed environment information and control the nonvolatile memory device according to the selected write mode. Accordingly, the nonvolatile memory device provides a write current for appropriate current consumption in a write operation.

摘要翻译： 提供了一种非易失性存储器件，具有该非易失性存储器件的存储器系统及其写入电流控制方法。 存储器系统包括非易失性存储器件和存储器控制器。 非易失性存储器件具有多个写入模式。 存储器控制器包括被配置为感测存储器系统的环境信息的传感器。 存储器控制器被配置为根据感测到的环境信息来选择写入模式之一并且根据所选择的写入模式来控制非易失性存储器件。 因此，非易失性存储器件在写入操作中提供用于适当电流消耗的写入电流。

公开(公告)号：US20090307415A1

公开(公告)日：2009-12-10

申请号：US12457238

申请日：2009-06-04

申请人： Yong-Hoon Kang ,  Ki Tae Park

发明人： Yong-Hoon Kang ,  Ki Tae Park

IPC分类号： G06F12/02 ,  G06F13/00

CPC分类号： G11C7/18 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/005 ,  G11C2216/14 ,  H01L27/11551

摘要： A memory device having a multi-layer structure, the memory device includes a first semiconductor layer including at least one memory cell array. The memory cell array includes a plurality of memory cells. A second semiconductor layer is on the first semiconductor layer. The second semiconductor layer includes a bit line and a page buffer connected to the bit line corresponding to the memory cell array. The memory device also includes a contact between the first semiconductor substrate and the second semiconductor substrate to connect the page buffer with the memory cell array.

摘要翻译： 一种具有多层结构的存储器件，所述存储器件包括包括至少一个存储单元阵列的第一半导体层。 存储单元阵列包括多个存储单元。 第二半导体层位于第一半导体层上。 第二半导体层包括连接到与存储单元阵列对应的位线的位线和页缓冲器。 存储器件还包括第一半导体衬底和第二半导体衬底之间的接触，以将页缓冲器与存储单元阵列连接起来。

公开(公告)号：US20090168511A1

公开(公告)日：2009-07-02

申请号：US12314651

申请日：2008-12-15

申请人： Yong-Hoon Kang

发明人： Yong-Hoon Kang

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/26

摘要： Disclosed is a flash memory device including a memory cell array having memory cells arranged at intersections of word lines and bit lines, such that one bit line is associated with a plurality of memory cells connected in series, a voltage generator configured to generate at least a first selection voltage, a row selection circuit configured to drive the non-selected word lines based on at least the first non-selected voltage, and a control logic circuit configured to control the voltage generator and the row selection circuit, such that the voltage generator generates at least the first non-selection voltage based on a location of a selected memory cell in the plurality of memory cells.

摘要翻译： 公开了一种闪速存储器件，其包括具有布置在字线和位线的交点处的存储器单元的存储单元阵列，使得一个位线与串联连接的多个存储单元相关联，电压发生器被配置为产生至少一个 第一选择电压，行选择电路，被配置为至少基于第一非选择电压驱动未选择的字线;以及控制逻辑电路，被配置为控制电压发生器和行选择电路，使得电压发生器 基于多个存储单元中所选存储单元的位置，至少产生第一非选择电压。

公开(公告)号：US06347169B1

公开(公告)日：2002-02-12

申请号：US09482541

申请日：2000-01-14

申请人： Yong-Hoon Kang ,  Byung-Jik Kim

发明人： Yong-Hoon Kang ,  Byung-Jik Kim

IPC分类号： G02B628

CPC分类号： H04B10/077 ,  H04B10/07955 ,  H04J14/02

摘要： An apparatus and method of monitoring multiple channel signals of a wavelength division multiplexing (WDM) signal in a WDM system. The optical signal monitoring apparatus includes: an optical demultiplexer having 2N+2 output ports, for receiving and demultiplexing by wavelength a wavelength division multiplexing (WDM) signal with N wavelengths, and outputting two output port signals for each channel via the 2N output ports and outputting two adjacent signals via the +2 output ports needed to measure the optical signal noise ratio outside the frequency range of the WDM signal; a signal conversion unit for receiving the output port signals from the optical demultiplexer and converting the received optical output port signals into digital signals; and a signal processing unit for receiving the digital signals and calculating the wavelength and optical power for each channel using the loss characteristics of the two output port signals of each channel. Therefore, the information about the multiple channel signals, such as the optical power, the wavelength and the optical signal to noise ratio (OSNR), can be simultaneously and accurately obtained by using the optical signal monitoring apparatus constructed as a small module.

摘要翻译： 一种在WDM系统中监视波分复用（WDM）信号的多信道信号的装置和方法。 光信号监视装置包括：具有2N + 2个输出端口的光解复用器，用于通过波长接收和解复用具有N个波长的波分复用（WDM）信号，并且经由2N个输出端口为每个信道输出两个输出端口信号，以及 通过+2个输出端口输出两个相邻信号，以测量WDM信号频率范围之外的光信号噪声比; 信号转换单元，用于从光解复用器接收输出端口信号并将接收到的光输出端口信号转换成数字信号; 以及信号处理单元，用于接收数字信号，并且使用每个通道的两个输出端口信号的损耗特性来计算每个通道的波长和光功率。 因此，通过使用构成小模块的光信号监视装置，可以同时且准确地获得关于多路信号的信息，如光功率，波长和光信噪比（OSNR）。

公开(公告)号：US08634225B2

公开(公告)日：2014-01-21

申请号：US13053337

申请日：2011-03-22

申请人： Yong-hoon Kang

发明人： Yong-hoon Kang

IPC分类号： G11C11/24

CPC分类号： G11C29/04 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2029/1204

摘要： A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell. A detection reference point is changed upon wear indication to detect the resistance of the resistive memory cell. The resistance of the resistive memory cell is detected using the changed detection reference point to determine whether or not the resistive memory cell is worn by comparing the detected resistance to a wear reference level.

公开(公告)号：US08111576B2

公开(公告)日：2012-02-07

申请号：US12620760

申请日：2009-11-18

申请人： Yong Hoon Kang

发明人： Yong Hoon Kang

IPC分类号： G11C7/02

CPC分类号： G11C5/145 ,  G11C13/0038 ,  H03K4/48

摘要： A high-voltage sawtooth current driving circuit and a memory device including the same are described. In the high-voltage sawtooth current driving circuit includes a charge pump circuit configured to output a first voltage, a regulating circuit configured to regulate a second voltage using the first voltage output from the charge pump circuit, and a sawtooth current driver configured to generate a sawtooth current in response to the second voltage regulated by the regulating circuit.

摘要翻译： 描述高压锯齿电流驱动电路和包括其的存储器件。 在高压锯齿电流驱动电路中，包括配置为输出第一电压的电荷泵电路，配置成使用从电荷泵电路输出的第一电压来调节第二电压的调节电路，以及锯齿电流驱动器， 响应于由调节电路调节的第二电压的锯齿波电流。

公开(公告)号：US08018777B2

公开(公告)日：2011-09-13

申请号：US12314651

申请日：2008-12-15

申请人： Yong-Hoon Kang

发明人： Yong-Hoon Kang

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/26

摘要： Disclosed is a flash memory device including a memory cell array having memory cells arranged at intersections of word lines and bit lines, such that one bit line is associated with a plurality of memory cells connected in series, a voltage generator configured to generate at least a first selection voltage, a row selection circuit configured to drive the non-selected word lines based on at least the first non-selected voltage, and a control logic circuit configured to control the voltage generator and the row selection circuit, such that the voltage generator generates at least the first non-selection voltage based on a location of a selected memory cell in the plurality of memory cells.

摘要翻译： 公开了一种闪速存储器件，其包括具有布置在字线和位线的交点处的存储器单元的存储单元阵列，使得一个位线与串联连接的多个存储单元相关联，电压发生器被配置为产生至少一个 第一选择电压，行选择电路，被配置为至少基于第一非选择电压驱动未选择的字线;以及控制逻辑电路，被配置为控制电压发生器和行选择电路，使得电压发生器 基于多个存储单元中所选存储单元的位置，至少产生第一非选择电压。