公开(公告)号：US20200152819A1

公开(公告)日：2020-05-14

申请号：US16724397

申请日：2019-12-23

申请人： Young-kwon JUN

发明人： Young-kwon JUN

IPC分类号： H01L31/18 ,  H01L31/0288 ,  H01L31/0216 ,  H01L31/0392 ,  H01L31/0336 ,  H01L31/032

摘要： A method for preparing a solar cell, includes: forming a first electrode on a substrate; forming a light absorbing layer on the first electrode; and forming a second electrode on the light absorbing layer, wherein the method further comprises forming an impurity material layer including an impurity element on the light absorbing layer adjacent to the first electrode or the second electrode in any one side or both sides thereof, and forming a doping layer by diffusing the impurity element into a portion of the light absorbing layer.

公开(公告)号：US20160126379A1

公开(公告)日：2016-05-05

申请号：US14896396

申请日：2014-03-18

申请人： Young Kwon JUN

发明人： Young Kwon JUN

IPC分类号： H01L31/0392 ,  H01L31/0749 ,  H01L31/18 ,  H01L31/0224

CPC分类号： H01L31/03923 ,  H01L31/022466 ,  H01L31/04 ,  H01L31/0749 ,  H01L31/18 ,  H01L31/1884 ,  Y02E10/541

摘要： Disclosed is a solar cell including a substrate, a back electrode, a light-absorbing layer, a buffer layer, and a front transparent electrode. The buffer layer includes a titanium (Ti) compound. The light-absorbing layer includes a compound composed of M1, M2, M3 (where M1 is copper (Cu), silver (Ag), or a combination thereof, M2 is indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), or a combination thereof, and M3 is selenium (Se), sulfur (S), or a combination thereof), and a combination thereof.

摘要翻译： 公开了一种太阳能电池，其包括基板，背面电极，光吸收层，缓冲层和前透明电极。 缓冲层包括钛（Ti）化合物。 光吸收层包括由M1，M2，M3（其中M1是铜（Cu），银（Ag）或它们的组合，M2是铟（In），镓（Ga），铝（Al） ，锌（Zn），锡（Sn）或其组合，M3是硒（Se），硫（S）或它们的组合）及其组合。

公开(公告)号：US6043149A

公开(公告)日：2000-03-28

申请号：US899210

申请日：1997-07-23

申请人： Young Kwon Jun

发明人： Young Kwon Jun

IPC分类号： H01L21/3205 ,  C23C16/16 ,  C23C16/18 ,  C23C16/56 ,  H01L21/304 ,  H01L21/768 ,  H01L23/522 ,  H01L21/70

CPC分类号： H01L21/76877 ,  C23C16/16 ,  C23C16/18 ,  C23C16/56

摘要： A method for forming a metal line of a semiconductor device includes the steps of: forming an insulating film on a semiconductor substrate including a lower layer line; forming a via hole to partially expose the lower layer line by selectively removing the insulating film; forming a first conductivity material layer on the insulating film including the via hole; forming a plug layer by selectively removing the first conductivity material layer so that it remains only in the via hole; performing a resistance-lowering treatment on the plug layer to remove its impurities; and forming a second conductivity material layer on the insulating film including the plug layer to form an upper layer line.

摘要翻译： 一种形成半导体器件的金属线的方法包括以下步骤：在包括下层线的半导体衬底上形成绝缘膜; 通过选择性地去除所述绝缘膜而形成通孔以部分地暴露所述下层线; 在包括通孔的绝缘膜上形成第一导电材料层; 通过选择性地去除第一导电材料层以使其仅保留在通孔中而形成插塞层; 对塞子层进行电阻降低处理以去除其杂质; 以及在包括所述插塞层的所述绝缘膜上形成第二导电材料层以形成上层线。

公开(公告)号：US5960313A

公开(公告)日：1999-09-28

申请号：US852293

申请日：1997-05-07

申请人： Young Kwon Jun

发明人： Young Kwon Jun

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L21/4763

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/528 ,  H01L2924/0002

摘要： A metal wire and a method for forming a metal wire of a semiconductor device, including the steps of forming an insulating layer and first etch-stop layer on a substrate forming a first trench having sidewalls and a bottom by selectively removing portions of said first etch-stop layer forming a second etch-stop layer on the insulating layer, including the first trench, and first-etch stop layer etching back said second etch-stop layer from within the trench to form a mask from said first and second etch-layers exposing a portion of the trench bottom, wherein the width of the mask has a width of less than the width of the trench bottom etching the insulating layer using said first and second etch-stop layers mask to form a second trench extending through the insulating layer for holding a contact plug removing said first and second etch-stop layers and forming a contact plug and conductive layer in said first and second trenches.

摘要翻译： 一种金属线和用于形成半导体器件的金属线的方法，包括以下步骤：通过选择性地去除所述第一蚀刻的部分，在形成具有侧壁和底部的第一沟槽的衬底上形成绝缘层和第一蚀刻停止层 所述第一蚀刻停止层在所述绝缘层上形成第二蚀刻停止层，所述第二蚀刻停止层包括所述第一沟槽，并且所述第一蚀刻停止层从所述沟槽内从所述沟槽中回蚀所述第二蚀刻停止层以从所述第一和第二蚀刻层形成掩模 暴露沟槽底部的一部分，其中掩模的宽度具有小于使用所述第一和第二蚀刻停止层掩模蚀刻绝缘层的沟槽底部的宽度的宽度，以形成延伸穿过绝缘层的第二沟槽 用于保持接触塞去除所述第一和第二蚀刻停止层，并在所述第一和第二沟槽中形成接触塞和导电层。

公开(公告)号：US5948705A

公开(公告)日：1999-09-07

申请号：US937589

申请日：1997-09-29

申请人： Young-Kwon Jun

发明人： Young-Kwon Jun

IPC分类号： H01L21/3213 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/00

CPC分类号： H01L21/76838

摘要： A method of forming an interconnection line of a semiconductor device includes the steps of forming an insulating layer on a substrate, forming a contact hole in the insulating layer, forming a first conductive material layer in the contact hole so that a top surface level of the first conductive material layer is the same as or higher than a top surface level of the insulating layer and so that a portion of the first conductive material layer remains on the insulating layer, and forming a second conductive material layer on the first conductive material layer as the portion of the first conductive material layer remaining on the insulating layer is removed.

摘要翻译： 形成半导体器件的互连线的方法包括以下步骤：在衬底上形成绝缘层，在绝缘层中形成接触孔，在接触孔中形成第一导电材料层， 第一导电材料层与绝缘层的顶表面水平相同或高于第一导电材料层的一部分保留在绝缘层上，并且在第一导电材料层上形成第二导电材料层，如 去除残留在绝缘层上的第一导电材料层的部分。

公开(公告)号：US5707274A

公开(公告)日：1998-01-13

申请号：US756559

申请日：1996-11-26

申请人： Yong-Kwon Kim ,  Young-Kwon Jun

发明人： Yong-Kwon Kim ,  Young-Kwon Jun

IPC分类号： B24B37/00 ,  B24B37/10 ,  B24B37/20 ,  B24B37/24 ,  B24B41/04 ,  H01L21/304 ,  B24B5/00

CPC分类号： H01L21/02024 ,  B24B37/04 ,  B24B41/04

摘要： A chemical mechanical polishing apparatus for a semiconductor wafer which is capable of polishing uniformly the surface of the semiconductor wafer and of controlling the polishing amount by providing plurality of rotary drums each wrapped in a polishing cloth on the upper surface of a polishing pad and connecting supporters capable of vertical movement to both ends each rotary drum, and includes a rotatable polishing pad in the planar upper surface of which a plurality of recesses are formed for receiving a semiconductor wafer, a plurality of rotatable polishing units located on the polishing pad for planarizing the surface of the semiconductor wafers, a supporter connected at the endpoints of the rotational polishing units which can make a vertical movement, and a slurry applicator located above the rotational polishing units for putting a slurry thereon.

摘要翻译： 一种用于半导体晶片的化学机械抛光装置，其能够均匀地研磨半导体晶片的表面，并且通过在抛光垫的上表面上设置多个旋转滚筒并将其包裹在研磨布上并连接支撑件 能够垂直移动到每个旋转鼓的两端，并且在其平面上表面中包括可旋转的抛光垫，其中形成有多个凹部用于接纳半导体晶片;多个可旋转的抛光单元，位于抛光垫上，用于将 半导体晶片的表面，连接在可以进行垂直运动的旋转抛光单元的端点处的支撑件，以及位于旋转抛光单元上方以在其上放置浆料的浆料施加器。

公开(公告)号：US5652169A

公开(公告)日：1997-07-29

申请号：US491209

申请日：1995-06-16

申请人： Young Kwon Jun

发明人： Young Kwon Jun

IPC分类号： B23K26/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5254 ,  H01L21/76894 ,  H01L2924/0002 ,  Y10S148/055

摘要： A programmable semiconductor element having an antifuse structure and a method for fabricating the same is disclosed. The fabrication method for a programmable semiconductor element having an antifuse structure includes processes for forming a first insulation film on a silicon substrate, forming a conductive material having a fixed width on the first insulation film, forming a second insulation film on the conductive material, forming a recess by etching a part of the second insulation film, forming a conductive link at corners of the recess in the second insulation film, forming a contact hole by etching the second insulation film in the recess thereof having no conductive link formed thereon, exposing the conductive material at a lower part, forming two separated conductors by etching the exposed conductive material, and forming a capping insulation film on the overall surface of the substrate and covering the conductive link.

摘要翻译： 公开了一种具有反熔丝结构的可编程半导体元件及其制造方法。 具有反熔丝结构的可编程半导体元件的制造方法包括在硅衬底上形成第一绝缘膜的工艺，在第一绝缘膜上形成具有固定宽度的导电材料，在导电材料上形成第二绝缘膜，形成 通过蚀刻所述第二绝缘膜的一部分而形成凹部，在所述第二绝缘膜的所述凹部的角部形成导电性接合部，通过在其上形成有导电性接合部的凹部中蚀刻所述第二绝缘膜而形成接触孔， 导电材料在下部，通过蚀刻暴露的导电材料形成两个分离的导体，并在基片的整个表面上形成覆盖导电连接的封盖绝缘膜。

公开(公告)号：US5461248A

公开(公告)日：1995-10-24

申请号：US205917

申请日：1994-03-03

申请人： Young-Kwon Jun

发明人： Young-Kwon Jun

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10829

摘要： A trench capacitor memory cell having a semiconductor substrate, an active region having a transistor on a portion of the semiconductor substrate, a field region formed by removing portion of the semiconductor substrate except for portions of the active region to a certain depth below the surface of the semiconductor substrate, a capacitor trench region formed in contact with a part of the active region and within the field region, and a polysilicon plug formed within the field region except for the trench region, and insulated by being surrounded by an insulating layer.

摘要翻译： 一种具有半导体衬底的沟槽电容器存储单元，在半导体衬底的一部分上具有晶体管的有源区，通过将有源区的部分除去部分以外的半导体衬底的部分去除在 所述半导体衬底，形成为与所述有源区的一部分并且在所述场区内接触的电容器沟槽区，以及形成在除所述沟槽区之外的所述场区内的多晶硅插塞，并被绝缘层包围。

公开(公告)号：US06544836B2

公开(公告)日：2003-04-08

申请号：US09840047

申请日：2001-04-24

申请人： Young-Kwon Jun

发明人： Young-Kwon Jun

IPC分类号： H01L218242

CPC分类号： G11C11/404 ,  H01L27/108

摘要： A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.

摘要翻译： 存储器件及其形成方法包括用于施加单元驱动信号的多个字线，用于输入或输出数据的多个位线，以及多个单元，每个单元具有第一栅极，源极和漏极，以及 第二栅极，其中第一栅极或第二栅极连接到字线之一，源电极连接到位线之一，漏电极连接到未连接到第一栅极的第一栅极或第二栅极 字线

公开(公告)号：US06365972B1

公开(公告)日：2002-04-02

申请号：US09431876

申请日：1999-11-02

申请人： Young Kwon Jun

发明人： Young Kwon Jun

IPC分类号： H01L2348

CPC分类号： H01L23/53238 ,  H01L21/768 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal wiring stricture includes a conduction line, an insulator film for electrically insulating the conduction line, and a transmutation layer formed as the density of a portion of the insulator film adjacent to the conduction line is increased or by adding impurities to the insulator film. A metal wiring forming method for a semiconductor device, includes the step of forming a trench in a given portion of a silicon oxidation film formed on a semiconductor substrate, forming a transmutation layer on a surface of the silicon oxidation film, and depositing a conductive material on the transmutation layer to form a conduction line, whereby diffusion of the conductive material is prevented.

摘要翻译： 金属布线狭窄包括导线，用于使导线电绝缘的绝缘膜，以及随着与导电线相邻的绝缘膜的一部分的密度而形成的变形层增加或者通过向绝缘膜添加杂质。 一种用于半导体器件的金属布线形成方法，包括在形成于半导体基板上的硅氧化膜的给定部分中形成沟槽的步骤，在硅氧化膜的表面上形成转化层，并沉积导电材料 在变换层上形成导线，从而防止导电材料的扩散。