公开(公告)号：US08123986B2

公开(公告)日：2012-02-28

申请号：US12279199

申请日：2007-06-26

Applicant: Jung Sok Noh ,  Young Woo Seo ,  Chang Min Han

Inventor： Jung Sok Noh ,  Young Woo Seo ,  Chang Min Han

IPC: H01B1/02

CPC classification number: H01J11/24 ,  C03C8/14 ,  C03C8/18 ,  H01J9/02 ,  H01J11/12 ,  H01J2211/225 ,  H01J2211/444

Abstract: A plasma display device and a method of manufacturing a plasma display panel (PDP) are provided. The method includes applying onto a substrate a black matrix paste for forming a black matrix and an electrode paste for forming an electrode; laminating a dielectric material on the substrate; and firing the black matrix paste, the electrode paste, and the dielectric material at the same time. Therefore, it is possible to simplify the manufacture of a PDP by firing electrodes, black matrices, and a dielectric material at the same time. In addition, it is possible to reduce the probability of the generation of air bubbles by appropriately reducing the amount of glass frit in a paste. Moreover, it is possible to enhance the efficiency of driving a PDP and the reliability of a plasma display device.

Abstract translation: 提供等离子体显示装置和制造等离子体显示面板（PDP）的方法。 该方法包括在基板上涂布用于形成黑色矩阵的黑色基质糊料和用于形成电极的电极浆料; 将介电材料层叠在基板上; 并同时烧制黑色基质糊剂，电极糊剂和电介质材料。 因此，可以通过同时烧制电极，黑矩阵和电介质材料来简化PDP的制造。 此外，通过适当地减少糊料中的玻璃料的量，可以降低产生气泡的可能性。 此外，可以提高驱动PDP的效率和等离子体显示装置的可靠性。

公开(公告)号：US5926707A

公开(公告)日：1999-07-20

申请号：US846075

申请日：1997-04-25

Applicant: Young-woo Seo

Inventor： Young-woo Seo

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC classification number: H01L27/10873 ,  H01L27/10808

Abstract: Methods of forming DRAM memory devices include the steps of forming deep storage electrode contact regions to improve the refresh characteristics of DRAM memory cells therein. In particular, the methods include the steps of forming an array of DRAM memory cells in a field ion region of second conductivity type. These memory cells contain storage electrode contact regions and bit line contact regions of first conductivity type therein. An electrically insulating layer is then deposited on the memory cells. Storage electrode contact holes are formed in the electrically insulating layer to expose the storage electrode contact regions. Dopants of first conductivity type are then implanted through the storage electrode contact holes and into the storage electrode contact regions at a first energy in a range between about 60 and 150 KeV. Then, dopants of first conductivity type are again implanted through the storage electrode contact holes at a second higher energy in a range between about 200 and 450 KeV. These dual implanting steps are preferably performed to define deep storage electrode contact extensions which extend through the field ion region and form nonrectifying junctions with the semiconductor substrate. These storage electrode contact extensions improve the refresh characteristics of the memory cells in the array by compensating for parasitic electric fields and etching damage in the field ion region.

Abstract translation: 形成DRAM存储器件的方法包括形成深存储电极接触区域以改善其中的DRAM存储器单元的刷新特性的步骤。 特别地，所述方法包括在第二导电类型的场离子区域中形成DRAM存储单元的阵列的步骤。 这些存储单元包含其中的第一导电类型的存储电极接触区域和位线接触区域。 然后将电绝缘层沉积在存储器单元上。 存储电极接触孔形成在电绝缘层中以暴露存储电极接触区域。 然后通过存储电极接触孔将第一导电类型的掺杂剂以约60至150KeV的范围内的第一能量注入存储电极接触区域。 然后，第一导电类型的掺杂剂通过存储电极接触孔再次以约200至450KeV的范围内的第二较高能量注入。 优选地进行这些双注入步骤以限定延伸穿过场离子区域并与半导体衬底形成非校正结的深存储电极接触延伸部。 这些存储电极接触延伸通过补偿场离子区域中的寄生电场和蚀刻损伤来改善阵列中的存储器单元的刷新特性。

公开(公告)号：US5751048A

公开(公告)日：1998-05-12

申请号：US553038

申请日：1995-11-03

Applicant: Yong Hee Lee ,  Young Woo Seo

Inventor： Yong Hee Lee ,  Young Woo Seo

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10873 ,  H01L21/76897

Abstract: A structure of a semiconductor device is disclosed whereby a gate insulating layer, a polycrystalline silicon layer, a tungsten silicide layer and a first insulating layer are formed on a semiconductor substrate. Gates are formed by the removal of the layers by dry etching, wherein the etch rate of the tungsten silicide layer is faster than the other layers, thereby forming an undercut region in the tungsten silicide layer. A second insulating layer is formed on the surface of the resultant structure to form spacers, and a contact window is formed between the gates via an etching process. The second insulating layer portion which forms the spacers need not be thick to prevent etching of the gates when forming the contact window, therefore good step coverage is achieved and reliability of the device is increased.

Abstract translation: 公开了半导体器件的结构，由此在半导体衬底上形成栅极绝缘层，多晶硅层，硅化钨层和第一绝缘层。 通过干蚀刻去除层形成栅极，其中硅化钨层的蚀刻速率比其他层更快，从而在硅化钨层中形成底切区域。 在所得结构的表面上形成第二绝缘层以形成间隔物，并且通过蚀刻工艺在栅极之间形成接触窗口。 形成间隔物的第二绝缘层部分不必是厚的，以防止在形成接触窗口时蚀刻栅极，因此实现了良好的阶梯覆盖，并且增加了器件的可靠性。

公开(公告)号：US5484739A

公开(公告)日：1996-01-16

申请号：US352248

申请日：1994-12-08

Applicant: Yong-hee Lee ,  Young-woo Seo ,  Jung-hyun Shin

Inventor： Yong-hee Lee ,  Young-woo Seo ,  Jung-hyun Shin

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/8244

CPC classification number: H01L27/10852 ,  H01L21/28512 ,  H01L27/0922 ,  H01L27/10873 ,  Y10S148/082

Abstract: A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation. In forming the second conductivity-type area, an additional insulating layer is formed, and using a mask pattern for exposing the second conductivity area, selectively and anisotropically etched so that the remaining insulating layer or the mask pattern for exposing the second conductivity-type area serves as an impurity-implantation preventing mask.

Abstract translation: 公开了一种半导体器件及其制造方法，其中用于固定接触边缘的连接焊盘层形成在第一导电类型区域上，而电极直接通过第二导电类型区域上的开口而不连接焊盘层。 在该方法中，在基板的整个表面上形成绝缘层。 使用用于暴露第一导电类型区域的掩模图案，将放置在暴露部分上的绝缘层进行各向异性蚀刻，使得剩余的绝缘层在随后的第一导电型杂质注入步骤中用作杂质注入防止掩模。 用于连接焊盘层的材料层在杂质注入步骤之前形成并且在杂质注入之后被图案化。 在形成第二导电类型区域时，形成另外的绝缘层，并且使用用于暴露第二导电区域的掩模图案进行选择性和各向异性蚀刻，使得用于暴露第二导电类型区域的剩余绝缘层或掩模图案 用作杂质注入防止掩模。

公开(公告)号：US5358888A

公开(公告)日：1994-10-25

申请号：US992905

申请日：1992-12-18

Applicant: Ji-hong Ahn ,  Young-woo Seo

Inventor： Ji-hong Ahn ,  Young-woo Seo

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/10817

Abstract: A method for manufacturing a capacitor of a highly integrated semiconductor memory device includes the steps of forming a conductive layer on the whole surface of a semiconductor substrate, forming a first material layer on the whole surface of the conductive layer, forming a polysilicon layer having hemispherical grains on the whole surface of the first material layer, forming a first material layer pattern by performing an etching on the first material layer, using the polysilicon layer as an etch-mask, partially removing the conductive layer by anisotropically etching the conductive layer, using the first material layer pattern as an etch-mask, defining the conductive layer into an individual unit cell, and removing the first material layer pattern. Since greater cell capacitance can be secured by a simple process, this method can be adopted to manufacturing semiconductor memory devices having packing densities up to 64 Mb and 256 Mb.

Abstract translation: 一种高度集成的半导体存储器件的电容器的制造方法，其特征在于，在半导体基板的整个表面形成导电层，在导体层的整个表面形成第一材料层，形成半导体层 晶粒在第一材料层的整个表面上，通过使用多晶硅层作为蚀刻掩模，在第一材料层上进行蚀刻形成第一材料层图案，通过各向异性蚀刻导电层来部分地去除导电层，使用 所述第一材料层图案作为蚀刻掩模，将所述导电层限定为单个单元电池，以及去除所述第一材料层图案。 由于可以通过简单的工艺来确保更大的电池电容，因此可以采用该方法制造具有高达64Mb和256Mb的封装密度的半导体存储器件。

公开(公告)号：US20090066248A1

公开(公告)日：2009-03-12

申请号：US12279199

申请日：2007-06-26

Applicant: Jung Sok Noh ,  Young Woo Seo ,  Chang Min Han

Inventor： Jung Sok Noh ,  Young Woo Seo ,  Chang Min Han

IPC: H01J17/49 ,  H01J9/00 ,  C09D1/00 ,  H01B1/12

CPC classification number: H01J11/24 ,  C03C8/14 ,  C03C8/18 ,  H01J9/02 ,  H01J11/12 ,  H01J2211/225 ,  H01J2211/444

Abstract: A plasma display device and a method of manufacturing a plasma display panel (PDP) are provided. The method includes applying onto a substrate a black matrix paste for forming a black matrix and an electrode paste for forming an electrode; laminating a dielectric material on the substrate; and firing the black matrix paste, the electrode paste, and the dielectric material at the same time. Therefore, it is possible to simplify the manufacture of a PDP by firing electrodes, black matrices, and a dielectric material at the same time. In addition, it is possible to reduce the probability of the generation of air bubbles by appropriately reducing the amount of glass frit in a paste. Moreover, it is possible to enhance the efficiency of driving a PDP and the reliability of a plasma display device.

Abstract translation: 提供等离子体显示装置和制造等离子体显示面板（PDP）的方法。 该方法包括在基板上涂布用于形成黑色矩阵的黑色基质糊料和用于形成电极的电极浆料; 将介电材料层叠在基板上; 并同时烧制黑色基质糊剂，电极糊剂和电介质材料。 因此，可以通过同时烧制电极，黑矩阵和电介质材料来简化PDP的制造。 此外，通过适当地减少糊料中的玻璃料的量，可以降低产生气泡的可能性。 此外，可以提高驱动PDP的效率和等离子体显示装置的可靠性。

公开(公告)号：US5981324A

公开(公告)日：1999-11-09

申请号：US956584

申请日：1997-10-23

Applicant: Young-woo Seo ,  Young-pil Kim ,  Myeon-koo Kang ,  Won-shik Lee

Inventor： Young-woo Seo ,  Young-pil Kim ,  Myeon-koo Kang ,  Won-shik Lee

IPC: H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10844 ,  H01L27/1052

Abstract: Methods of forming integrated circuits having memory cell arrays therein and peripheral circuits therein include the steps of selectively forming more lightly doped source and drain regions for transistors in the memory cell arrays. These more lightly doped source and drain regions are designed to have fewer crystalline defects therein caused by ion implantation, so that storage capacitors coupled thereto have improved refresh characteristics. Preferred methods include the steps of forming a first well region of first conductivity type (e.g., P-type) in a memory cell portion of a semiconductor substrate and a second well region of first conductivity type in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion. First and second insulated gate electrodes are then formed on the first and second well regions, respectively, using conventional techniques. First dopants of second conductivity type are then implanted at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask. These dopants are then diffused to form lightly doped source and drain regions adjacent the first and second insulated gate electrodes. Second dopants of second conductivity type are then selectively implanted at a second dose level, greater than the first dose level, into the second well region using self-alignment techniques. However, these dopants are preferably not implanted into the first well region. These second dopants are then diffused into the second source/drain regions.

Abstract translation: 形成其中具有存储单元阵列的集成电路及其外围电路的方法包括以下步骤：为存储单元阵列中的晶体管选择性地形成更多的轻掺杂源极和漏极区域。 这些更轻掺杂的源极和漏极区域被设计为在离子注入中具有较少的晶体缺陷，使得与其耦合的存储电容器具有改善的刷新特性。 优选的方法包括以下步骤：在半导体衬底的存储单元部分中形成第一导电类型的第一阱区域（例如，P型）和在半导体衬底延伸的外围电路部分中的第一导电类型的第二阱区域 邻近存储单元部分。 然后使用常规技术分别在第一和第二阱区上形成第一和第二绝缘栅电极。 然后使用第一和第二绝缘栅电极作为植入掩模，将第一导电类型的第一掺杂剂以第一剂量水平注入第一阱区和第二阱区。 然后这些掺杂剂被扩散以形成与第一和第二绝缘栅电极相邻的轻掺杂源极和漏极区。 然后使用自对准技术将第二导电类型的第二掺杂剂以大于第一剂量水平的第二剂量水平选择性地植入第二阱区。 然而，这些掺杂剂优选不被植入第一阱区。 然后将这些第二掺杂剂扩散到第二源/漏区。

公开(公告)号：US6080613A

公开(公告)日：2000-06-27

申请号：US764202

申请日：1996-12-13

Applicant: Young-woo Seo ,  Dug-dong Kang ,  Sun-cheol Hong ,  Won-cheol Hong

Inventor： Young-woo Seo ,  Dug-dong Kang ,  Sun-cheol Hong ,  Won-cheol Hong

IPC: H01L21/265 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC classification number: H01L27/10873 ,  H01L27/10808

Abstract: Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type. Contact regions of first conductivity type for a storage electrode and bit line are then formed at the same time at adjacent opposing edges of the word lines by implanting dopants of first conductivity type into the region of second conductivity type using the word line as an implant mask. A storage electrode of a capacitor is then formed on (or coupled to) the storage electrode contact region adjacent a first edge of the word line and a bit line is also preferably formed on (or coupled to) the bit line contact region adjacent a second edge of the word line. The bit line contact region and storage electrode contact region preferably receive a double dose of first conductivity type dopants by performing a first ion implant step, forming sidewall spacers on the first and second edges of the word line and then performing a second ion implant step using the sidewall spacers as an implant mask.

Abstract translation: 形成诸如DRAM存储单元的集成电路存储器件的方法包括在第二导电类型的半导体区域中同时形成第一导电类型的存储电极和位线接触区的步骤。 接触区优选地接收双剂量的第一导电类型的掺杂剂。 该双剂量补偿了在处理过程中造成的蚀刻损伤，并提高了存储单元的刷新特性。 形成DRAM存储单元的优选方法包括以下步骤：在包含延伸到面部的第二导电类型区域（例如，P型）的半导体衬底的表面上形成电绝缘层，然后形成字线 （或其片段）在与第二导电类型的区域相反的电绝缘层上。 然后通过将第一导电类型的掺杂剂注入到第二导电类型的区域中，使用字线作为植入掩模，在相邻的字线的相对边缘处同时形成用于存储电极和位线的第一导电类型的接触区域 。 然后，在与字线的第一边缘相邻的存储电极接触区域上形成电容器的存储电极（或耦合到）存储电极接触区域，并且位线也优选地形成在邻近第二个位线的位线接触区域（或耦合到）位线接触区域 字线的边缘。 位线接触区域和存储电极接触区域优选地通过执行第一离子注入步骤接收双剂量的第一导电类型掺杂剂，在字线的第一和第二边缘上形成侧壁间隔物，然后使用 侧壁间隔件作为植入物掩模。

公开(公告)号：US5818091A

公开(公告)日：1998-10-06

申请号：US747378

申请日：1996-11-12

Applicant: Yong-hee Lee ,  Young-woo Seo ,  Jung-hyun Shin

Inventor： Yong-hee Lee ,  Young-woo Seo ,  Jung-hyun Shin

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/76 ,  H01L23/48 ,  H01L29/94 ,  H01L31/06

CPC classification number: H01L27/10852 ,  H01L21/28512 ,  H01L27/0922 ,  H01L27/10873 ,  Y10S148/082

Abstract: A semiconductor device includes a connection pad layer for securing a contact margin which is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. A device fabricated according to this structure yields improved punch-through and junction depth characteristics.

Abstract translation: 半导体器件包括用于固定形成在第一导电类型区域上的接触边缘的连接焊盘层，而电极通过第二导电类型区域上的开口直接连接，而没有连接焊盘层。 根据该结构制造的器件产生改善的穿通和结深度特性。

公开(公告)号：US5545578A

公开(公告)日：1996-08-13

申请号：US440954

申请日：1995-05-15

Applicant: Young-hoon Park ,  Young-woo Seo ,  Yong-hee Lee

Inventor： Young-hoon Park ,  Young-woo Seo ,  Yong-hee Lee

IPC: H01L21/328 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6659 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/6656

Abstract: A method for manufacturing a semiconductor device, e.g., an LDD transistor, which includes the steps of forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the gate insulating layer, forming a silicide layer on the polysilicon layer, etching the silicide layer to form a gate-patterned silicide layer, and over-etching the silicide layer to partially etch the polysilicon layer, to thereby form a step in the polysilicon layer, forming an oxidation-prevention spacer on sidewalls of the gate-patterned silicide layer and sidewalls of the polysilicon layer exposed by the step, etching the polysilicon layer, using the oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, the gate-patterned silicide layer and the gate-patterned polysilicon layer together comprising a gate electrode, thermally oxidizing exposed portions of the gate insulating layer and exposed portions of the polysilicon layer, to thereby form an oxide layer, and, ion-implanting impurities into the semiconductor substrate, using the resultant structure as an ion-implantation mask, to thereby form source/drain regions in the semiconductor substrate, on opposite sides of the gate electrode.

Abstract translation: 一种制造半导体器件的方法，例如LDD晶体管，其包括以下步骤：在半导体衬底上形成栅极绝缘层，在栅绝缘层上形成多晶硅层，在多晶硅层上形成硅化物层，蚀刻 硅化物层以形成栅极图案化硅化物层，并且过蚀刻硅化物层以部分蚀刻多晶硅层，从而在多晶硅层中形成步骤，在栅极图案化硅化物层的侧壁上形成防氧化间隔物 和通过该步骤暴露的多晶硅层的侧壁，使用防氧化间隔物作为蚀刻掩模蚀刻多晶硅层，从而形成栅极图案化多晶硅层，栅极图案化硅化物层和栅极图案化多晶硅层 一起包括栅电极，热氧化栅极绝缘层的暴露部分和多晶硅层的暴露部分，从而形成 氧化物层，以及使用所得结构作为离子注入掩模将杂质离子注入到半导体衬底中，从而在栅电极的相对侧上形成半导体衬底中的源极/漏极区。