中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

56 records (took 0.015 seconds)

    MINIMIZING CROSSTALK IN A DATA TRANSFER DEVICE
    1.
    发明申请
    MINIMIZING CROSSTALK IN A DATA TRANSFER DEVICE 有权
    在数据传输设备中最小化CROSSTALK

    公开(公告)号：US20150223321A1

    公开(公告)日：2015-08-06

    申请号：US13977057

    申请日：2011-12-21

    Applicant: Yun Ling

    Inventor： Yun Ling

    IPC: H05K1/02 ,  H05K3/30

    CPC classification number: H05K1/0228 ,  H01R13/6461 ,  H01R13/6471 ,  H04L25/0274 ,  H05K3/30 ,  Y10T29/49133

    Abstract: Systems and methods provided may involve arranging a first differential pair and a second differential pair and adjusting spacing arrangements between the first differential pair and the second differential pair to minimize crosstalk.

    Abstract translation: 所提供的系统和方法可以包括布置第一差分对和第二差分对并且调整第一差分对和第二差分对之间的间隔布置以最小化串扰。

    SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR 审中-公开
    带有DOPED晶体管的半导体器件

    公开(公告)号：US20080087958A1

    公开(公告)日：2008-04-17

    申请号：US11951833

    申请日：2007-12-06

    Applicant: Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    Inventor： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    IPC: H01L27/088

    CPC classification number: H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

    Abstract translation: 半导体器件提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

    Stacked connectors for high density external cable connections
    5.
    发明申请
    Stacked connectors for high density external cable connections 审中-公开
    用于高密度外部电缆连接的堆叠连接器

    公开(公告)号：US20070232132A1

    公开(公告)日：2007-10-04

    申请号：US11393169

    申请日：2006-03-29

    Applicant: Yun Ling ,  Daniel Tong

    Inventor： Yun Ling ,  Daniel Tong

    IPC: H01R13/66

    CPC classification number: H01R12/716 ,  H01R12/75 ,  H01R27/02

    Abstract: A method and apparatus to couple one unified display interface (UDI) connector with another connector, such that the UDI connector is coupled between the other connector and a circuit board, such as a motherboard or add-in card. The UDI connector may be coupled to other I/O connectors, for example a VGA connector. The UDI connector may be coupled to one or more UDI connectors. The coupled connectors may have the same molded connector assembly and may have an integrated metal shell. On the source or host-end, two or more UDI plug connectors are made on the same cable over-mold to place the plug connectors closely to each other, minimizing the height of the coupled connectors. The cable exiting the multi-plug over-mold may be separated and attached to individual UDI plug connectors, connecting multiple monitors. Both ends of the cable may have multi-plugs in the same over-mold at each end. Such a cable may be used to support additional UDI lanes for higher bandwidths.

    Abstract translation: 将一个统一显示接口（UDI）连接器与另一连接器耦合的方法和装置，使得UDI连接器耦合在另一个连接器和电路板（例如主板或附加卡）之间。 UDI连接器可以耦合到其它I / O连接器，例如VGA连接器。 UDI连接器可以耦合到一个或多个UDI连接器。 耦合的连接器可以具有相同的模制连接器组件，并且可以具有集成的金属外壳。 在源端或主机端，两个或多个UDI插头连接器在相同的电缆外模上制成，以将插头连接器彼此靠近，使耦合的连接器的高度最小化。 离开多插头超模的电缆可以分离并连接到单独的UDI插头连接器，连接多个显示器。 电缆的两端可以在两端的同一个外模上具有多插头。 这样的电缆可以用于支持用于更高带宽的附加UDI通道。

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD 有权
    半导体器件和制造方法

    公开(公告)号：US20060252188A1

    公开(公告)日：2006-11-09

    申请号：US10908328

    申请日：2005-05-06

    Applicant: Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    Inventor： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    IPC: H01L21/84 ,  H01L21/00

    CPC classification number: H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

    Abstract translation: 用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE
    10.
    发明申请
    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE 有权
    使用膜的间隙轮廓工程，从内部到外表面连续增加的刻蚀速率

    公开(公告)号：US20130187202A1

    公开(公告)日：2013-07-25

    申请号：US13353684

    申请日：2012-01-19

    Applicant: Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    Inventor： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L29/6653 ,  H01L29/6656

    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

    Abstract translation: 通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加 从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。 实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

Patent Agency Ranking